WCET 2013 - Twelth International Workshop on Worst-Case Execution Time Analysis

The growing complexity of modern hardware, the advent of multicore processors, and the intricate organization of long-lived software systems challenge the results achieved by timing analysis techniques, for users and researchers alike.
Design principles for the construction of timing-composable systems at both hardware and software level (compiler, runtime and development method) are sought for timing analysis to respond to the emerging needs.
On this account, the workshop especially solicits contributions that:
discuss the limits of state-of-the-art timing analysis against aggressive hardware and software organizations, including but not limited to multicore systems, from both the research and the industrial perspectives;
present research results and research directions in timing analysis, and the system-level hardware and software support for it, that address the challenges ahead.
As part of and in addition to that, the workshop welcomes submissions that address:
Novel approaches to WCET computation and strategies to reduce the analysis complexity, including time-predictable computer architectures and synergy with compilers
Advances in tools for WCET analysis
Capturing flow facts to feed flow analysis for WCET
Needs and constraints stemming from current and future industrial development process and schedule that timing analysis should best accommodate
WCET-related analyses of code generated from design models
Experience with the integration of WCET with schedulability analysis, as well as with the software and system development process
Methods and benchmarks for WCET analysis evaluation.