JWAC 2012 - Third JILP Workshop on Architecture Competitions: Memory Scheduling Championship

The workshop on computer architecture competitions is a forum for holding competitions to evaluate computer architecture research topics. The third workshop is organized around a competition for memory scheduling algorithms. The Memory Scheduling Championship (MSC) invites contestants to submit their memory scheduling code to participate in this competition. Contestants must develop algorithms to optimize multiple metrics on a common evaluation framework provided by the organizing committee.
Objective
The goal for this competition is to compare different memory scheduling algorithms in a common framework. Algorithms will be evaluated in three tracks: (1) Delay (or Performance), (2) Energy-Delay Product (EDP), (3) Performance-Fairness Product (PFP).
Prizes
The best entry in each track will receive a trophy commemorating the triumph (OR some other prize to be determined later). Top submissions will be invited to present at the workshop, when results will be announced. All source code, write-ups and results will be made publicly available through the JWAC-3 website. Authors of accepted workshop papers will be invited to submit full papers for possible inclusion in a special issue of the Journal of Instruction-Level Parallelism (JILP). Inclusion in the special issue will depend on the outcome of JILP's peer-review process: invited papers will be held to the same standard as regular submissions.
Submission Requirements
Each contestant is allowed a maximum of three submissions to the competition. Each submission should include the following:
Abstract: A 300-word abstract summarizing the submission. In addition, the abstract should include the competition track for the submission, author names, their affiliations, and the email address of the contact author.
Paper: This will be a conference-quality write-up of the memory scheduling algorithm, including references to relevant related work. The paper must clearly describe how the algorithm works, how it is practical to implement, and how it conforms to the contest rules. The paper must be written in English and formatted as follows: no more than six pages, single-spaced, two-column format, minimum 10pt Times New Roman font. The paper should be submitted in .pdf format, and should be printable on letter-size paper with one-inch margins on all sides. A submission will be disqualified if the paper does not clearly describe the algorithm that corresponds to the submitted code. Papers that do not conform to the length and format rules will only be reviewed at the discretion of the program committee. For contestants with more than one submission, papers need to be sufficiently different, and not variations of the same basic idea. If papers are variations on the same idea, contestants should only submit the version that has the best results.
Results: The paper should include a table that summarizes results of the memory scheduling algorithm for the distributed program traces (this will be verified independently by the organizing committee).
Memory Scheduling Code: Two files (scheduler.c and scheduler.h) that contain the scheduler code. This code should be well commented so that it can be understood and evaluated. Unreadable or insufficiently documented code will be rejected by the program committee. The code should be compiled and run on the existing infrastructure without changing any code or Makefile, and should NOT require any library code that is not part of C. All code should be in ANSI C and POSIX conformant. We will compile the code using GCC version 4.4.3 (or higher) on a 64-bit GNU/Linux system, and if we can't compile and run the code, we can't evaluate the predictor.