FASPP 2012 - Second Workshop on Future Architectural Support for Parallel Programming

The ever-growing prevalence of parallel architectures has pushed the inherent difficulties in parallel programming to the front stage, and has stimulated research into novel parallel programming models. However, newly gained knowledge on parallel programming has yet to trickle down to modern architectures, and new manycore chips can largely still be viewed as arrays of sequential processors. In this workshop, we focus at exploring the parallel programmability issue from an architectural perspective. It is our goal to bring together experts in computer architectures, parallel programming, parallel algorithms, and parallel system design, and foster a discussion on the design of future parallel architectures by raising two fundamental questions:
What parallel abstractions should the hardware provide?
Which should be the responsability / functionality of the programmer, the runtime software, and the hardware?
We solicit position papers addressing the above questions with respect to all architectural aspects of parallel programming, and specifically:
enabling future parallel programming models
innovative architectural execution models
novel memory hierarchies
simplified and scalable memory models
high-level constructs for on-chip communications
characterization of the runtime overheads of parallel applications
future directions in programming massively parallel systems
potential bottlenecks for future parallel systems
FASPP is intended for quick publication of position papers, early results, and work-in-progress, and is not intended to prevent later publication of extended papers. Proceedings with accepted papers will be made available at the workshop and online.
In addition to paper presentations, the workshop will also host a keynote and a panel of experts in computer architecture and parallel programming who will debate the future of parallel architectures.