caos 2011 - Second Workshop on Computer Architecture and Operating System co-design

Second Workshop on

Computer Architecture and Operating System
co-design

In conjunction with:
the 6th ACM International Conference on
High-Performance Embedded Architectures and Compilers (HiPEAC'11)
Heraklion, Crete, Greece, January 24-26, 2011

Multi-core and/or multi-threaded architectures are monopolizing the market, from embedded systems to supercomputers. However, extracting high performance from these modern systems has become a complex task. As the number of cores per chip and/or the number of hardware threads per core continue to increase, new research questions arise in scheduling, power, temperature, scalability, design complexity, efficiency, throughput, heterogeneity, etc. Performance is not the only important metric anymore, and new metrics (such as security, power, total throughput, reliability and Quality of Service) are becoming more and more important. Therefore, it is evident that neither hardware nor software alone can achieve the desired performance and, at the same time, be compliant with these constraints. One approach to tackle these new challenges comes from hardware-software co-design.

This workshop aims to bring together researchers and engineers from academia and industry to share ideas and research directions in Computer Architecture and Operating System co-design and interaction. Authors are invited to submit innovative manuscripts in all areas of parallel and distributed processing, real-time systems, HPC systems and commercial/server systems.

Topics of interest

Papers are sought on topics including, but not limited to:

Architectural and OS support for power and thermal management
Architectural and OS support for scheduling applications on emerging multi-core systems
Benchmarking and characterization of OS activity in multi-core architectures
Architectural and OS support for virtualization
Architectural and OS support to manage processor resource allocation and heterogeneity for Quality of Service
Simulation tools for full system simulation
The workshop provides a forum to discuss the latest proposals in co-designing the computer architecture, software systems and OS and to bring ideas and research problems to the attention of the audience. Papers reporting on on-going work that address cross-cutting issues and provide thought-provoking insights into the main themes are encouraged to submit their work. Position and Vision papers are also welcomed. Papers Proceedings with accepted papers will be made available at the workshop and possible indexing with ACM. All Accepted papers will be considered for a best paper award, which will be announced at the workshop and the best paper will be considered for publication in a special issues of the HiPEAC workshop proceedings.

Program

TBD

Important dates

Abstracts submission deadline: new deadline Oct. 29th 2010 11:30PM PST
Papers submission deadline: new deadline Oct. 31th 2010 11:30PM PST
Notification to authors: Dec. 6th 2010
Final version of accepted papers: Dec. 20th 2010
HiPEAC Conference: Jan 24-26th, 2011
Workshop: Jan 22nd, 2011
Paper submission

Submitted papers should use the LNCS format and should be 10 pages maximum. Manuscript preparation guidelines can be found at the LNCS web site.
In order to submit your paper go to Here .

Workshop Co-Chairs

Roberto Gioiosa Barcelona Supercomputing Center Spain roberto.gioiosa[_at_]bsc.es
Lamia Youseff MIT, CSAIL USA lyouseff[_at_]csail.mit.edu
Workshop Publicity & Publication Chair

Omer Khan MIT, CSAIL USA okhan[_at_]csail.mit.edu
Program committee

Buyuktosunoglu, Alper (IBM T.J. Watson, USA)
Cazorla, Francisco (BSC, Spain)
Cesati, Marco (U. of Rome Tor Vergata, Italy)
da Silva, Dilma (IBM T.J. Watson, USA)
Etsion, Yoav (Barcelona Supercomputing Center, Spain)
Hoffmann, Henry (MIT, USA)
Holt, Jim (Freescale, USA)
Kursun, Eren (IBM T.J. Watson, USA)
McKee, Sally (Chalmers University of Technology, Sweden)
Minnich, Ronald (Sandia National Lab, USA)
Pakin, Scott (LANL, USA)
Tsafrir, Dan (Technion, Israel)
Villa, Oreste (PNNL, USA)
Wisniewski, Robert (IBM T.J. Watson, USA)