RAPIDO 2011 - 3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools

3rd Workshop on:
Rapid Simulation and Performance Evaluation: Methods and Tools
Saturday 22 Jan 2011

Held in conjunction with

the 6th International Conference on High-Performance and
Embedded Architectures and Compilers (HiPEAC)

Heraklion, Crete, Greece, January 24-26, 2011

Home Call for papers Committees Program Previous editions Registration Venue

The focus of the RAPIDO’11 workshop is on methods and tools for rapid simulation and performance evaluation in embedded and high performance systems design. Given continuous advances in chip technology, it is to be expected that future-generation processors will integrate numerous units on a single die, including multiple processor cores, multiple levels of (shared/private) caches or memories, and multiple dedicated accelerators, which will be glued together through a network on-chip (NoC).
The design space is huge though:

? How many cores do we need?

? Should we have a homogeneous or a heterogeneous design?

? When dynamic reconfiguration must be performed?

? How many caches/memories do we need?

? How to choose the instruction set(s) for these cores?

? What are the best code optimizations for a given application?

? How to combine the different metrics (e.g. energy, latency and throughput) into a global search space?

All these design questions lead to a huge design space that needs to be explored and which poses a grand challenge to search this space and to deliver an optimal design within the tight time-to-market budget.
In the embedded domain, the Intellectual Property (IP) based design approach is one of the most popular solutions to overcome this design challenge by relying on parameterized, pre-designed and pre-verified IP cores. Simulators are then used to explore the huge design space of interconnected IP cores for finding the optimal design for a given application domain.
In the general-purpose computing domain, the time-to-market is typically longer, the design is typically not limited to interconnecting pre-existing IP cores, however, the design should be optimized for a broader set of applications.
In both the embedded and the general-purpose domains, searching the huge design space during the design process is done through Design Space Exploration (DSE). DSE involves a number of key technologies such as modeling, simulation, prototyping, heuristic searching, etc. which have to cooperate in order to make the exploration effective, i.e., to obtain a final design with an optimal performance/power/cost/reliability ratio for the application domain of interest without compromising the time-to-market.
Although DSE is essential to both embedded and general-purpose processor design, both communities are largely unaware of each other’s work and progress. The purpose of this workshop therefore is to bridge this gap, and bring together researchers and practitioners from both communities to learn and discuss recent progress, and stimulate the interaction between both communities by exchanging ideas and sharing experiences. The workshop should provide a forum for brainstorming and road-mapping future DSE technologies for both the embedded and general-purpose domains.