HPPAC 2017 - Workshop on High-Performance Power-Aware Computing (HPPAC)

Power and energy are now recognized as first-order constraints
in high-performance computing. Optimizing performance under power
and energy bounds requires coordination across not only the software
stack (compilers, operating and runtime systems, job schedulers) but
also coordination with cooling systems and outwards to electrical
suppliers. As we continue to move towards exascale and extreme scale
computing, understanding how power translates to performance
becomes an increasingly critical problem.
The purpose of this workshop is to provide a forum where cutting-edge
research in the above topic can be shared with others in the community.
As such, while we welcome full (10 page) papers as in previous years,
we are now also soliciting short papers (4 pages max). While both should
conform to the list of topics below, short papers will be judged primarily
on their interest to the community. As such, these may be position papers,
initial results, open problems, software announcements, or interesting
work that does not reach the level of a full-paper treatment.
All papers will be subject to single-blind peer review, and the quality of
both the short and standard papers is expected to be high.
Topics of particular interest include (but are not limited to):
* Performance optimization across node, job, cluster and site power bounds.
* Power/performance tradeoffs across accelerators, processors and DRAM.
* Cooling/performance tradeoffs.
* Translating budgetary bounds into power and energy bounds.
* Efficient system design, from computer center to silicon
* Effects of compiler optimizations on code power and energy efficiency
* Power- and energy-aware job schedulers, runtime systems and operating systems.
* Models of power and performance, from processors to computer centers.
* Evaluations of hardware power and energy controls