HADM 2015 - 2015 International Workshop on Hardware Accelerated Data Mining
Date2015-11-13
Deadline2015-07-20
VenueAtlantic City, NJ, USA - United States
Keywords
Websitehttps://volga.usc.edu/hadm
Topics/Call fo Papers
The objective of this workshop is to investigate opportunities in accelerating data mining tasks over increasingly complex workloads (e.g., Petabytes of networked-data under real-time constraints) using emerging hardware accelerators (e.g., commodity and specialized Multi-core, GPUs, FPGAs, and ASICs) and corresponding programming models (e.g., MapReduce, GraphLab, CUDA, OpenCL, and OpenACC).
The use of hardware accelerators for mining high-rate data streams is becoming common mainly due to the rapidly increasing amount of data available for real-time analytics. The idea of using special-purpose hardware to accelerate computation has a long tradition in data processing but has thus far not made its way into mainstream data mining. The reason is two-fold: (i) hardware accelerators are relatively different to program, and (ii) data mining tasks are becoming increasingly data-intensive, which makes moving computation to a dedicated hardware accelerator costly. Moreover, CPU clock speeds have stagnated while parallelization and "smart" utilization of specialized hardware have emerged as the most promising method to improve performance. New memory technologies such as 3D DRAM stacks enable processing near memory architectures.
Utilizing these new hardware technologies and programming paradigms for efficient Data Mining is of urgent importance. However, many essential issues in this area have yet to be explored. For instance, graph computations are becoming prolific for mining large datasets in many fields. However, real-world graph data is sparse and highly non-uniform. Graph structure mining algorithms exhibit weak spatial locality when processing graphs with power law distributions and therefore such algorithms are both data-intensive and cache-hostile.
The aim of this workshop is to provide a venue for designers, practitioners, researchers, developers, and industrial/governmental partners to come together, present and discuss leading research results, use cases, innovative ideas, challenges, and opportunities that arise from accelerating mining of big data using new hardware, and identify future directions and challenges in this area.
The use of hardware accelerators for mining high-rate data streams is becoming common mainly due to the rapidly increasing amount of data available for real-time analytics. The idea of using special-purpose hardware to accelerate computation has a long tradition in data processing but has thus far not made its way into mainstream data mining. The reason is two-fold: (i) hardware accelerators are relatively different to program, and (ii) data mining tasks are becoming increasingly data-intensive, which makes moving computation to a dedicated hardware accelerator costly. Moreover, CPU clock speeds have stagnated while parallelization and "smart" utilization of specialized hardware have emerged as the most promising method to improve performance. New memory technologies such as 3D DRAM stacks enable processing near memory architectures.
Utilizing these new hardware technologies and programming paradigms for efficient Data Mining is of urgent importance. However, many essential issues in this area have yet to be explored. For instance, graph computations are becoming prolific for mining large datasets in many fields. However, real-world graph data is sparse and highly non-uniform. Graph structure mining algorithms exhibit weak spatial locality when processing graphs with power law distributions and therefore such algorithms are both data-intensive and cache-hostile.
The aim of this workshop is to provide a venue for designers, practitioners, researchers, developers, and industrial/governmental partners to come together, present and discuss leading research results, use cases, innovative ideas, challenges, and opportunities that arise from accelerating mining of big data using new hardware, and identify future directions and challenges in this area.
Other CFPs
- Symposium on Massive MIMO and Full-Dimension MIMO (FD-MIMO) Communications
- Symposium on Signal Processing and Mathematical Modeling of Biological Processes with Applications to Cyber-Physical Systems for Precise Medicine
- Symposium on Signal Processing Applications in Smart Buildings
- Symposium on Signal Processing for Optical Wireless Communications
- Symposium on Real-Time Signal Processing for Low-Cost and Low-Power Smart Devices
Last modified: 2015-05-07 23:02:52