CMAS 2015 - First TCRTS Workshop on Certifiable Multicore Avionics Systems (CMAS)
Topics/Call fo Papers
Multicore computer platforms pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory, I/O bandwidth and interconnections. Much of the real time scheduling for single core chips has centered on the CPU, because it has been the bottleneck resource. The emergence of multicore architectures has moved bottleneck resource away from CPU and towards the now globally shared memory, last level cache, and communication infrastructure.
Temporal coupling among concurrently running applications on different cores makes certification of safety-critical systems particularly challenging. Such problem has been recognized by the Certification Authorities Software Team (CAST), an international group of avionics certification and regulatory representatives from North and South America, Europe, and Asia. In particular, in May of this year CAST released Position Paper 32 on Multi-Core Processors (MCP, see CAST-32) to discuss topics related to safety of avionics software on multicore systems. Among other issues, the position paper identifies MCP Interference Channels, such as shared memory, cache and interconnect features, as possible sources of safety violations. While the position paper does not constitute binding policy on certification, it nevertheless strongly suggests that all such sources of interference must be:
identified;
analyzed;
certifiably mitigated.
Inspired by the CAST-32 position paper, the goal of the workshop is to bring together the Real-Time Systems (RTS) community to address the challenges in the certification of multicore avionics systems. In particular, we will seek contributions from the community on how to analyze and mitigate the effects of interference channels in Commercial-Off-The-Shelf (COTS) multicore processors. Major goals involve:
identify the set of timing-related challenges to be addressed;
determine which solutions are available for such challenges, and whether the community agrees on a set of such solutions;
determine which challenges remain as open problems and
The development of an evidence based validation and certification procedure.
Temporal coupling among concurrently running applications on different cores makes certification of safety-critical systems particularly challenging. Such problem has been recognized by the Certification Authorities Software Team (CAST), an international group of avionics certification and regulatory representatives from North and South America, Europe, and Asia. In particular, in May of this year CAST released Position Paper 32 on Multi-Core Processors (MCP, see CAST-32) to discuss topics related to safety of avionics software on multicore systems. Among other issues, the position paper identifies MCP Interference Channels, such as shared memory, cache and interconnect features, as possible sources of safety violations. While the position paper does not constitute binding policy on certification, it nevertheless strongly suggests that all such sources of interference must be:
identified;
analyzed;
certifiably mitigated.
Inspired by the CAST-32 position paper, the goal of the workshop is to bring together the Real-Time Systems (RTS) community to address the challenges in the certification of multicore avionics systems. In particular, we will seek contributions from the community on how to analyze and mitigate the effects of interference channels in Commercial-Off-The-Shelf (COTS) multicore processors. Major goals involve:
identify the set of timing-related challenges to be addressed;
determine which solutions are available for such challenges, and whether the community agrees on a set of such solutions;
determine which challenges remain as open problems and
The development of an evidence based validation and certification procedure.
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Last modified: 2015-04-09 22:26:43