AASC 2015 - International Workshop on Architecture-aware Simulation and Computing (AASC 2015)

With multi- and many-core based systems, performance increase on the microprocessor side will continue according to Moore's Law, at least in the near future. However, the already existing performance limitations due to slow memory access are expected to get worse with multiple cores on a chip, and complex hierarchies of cache memory will make it hard for users to fully exploit the theoretically available performance. In addition, the increasingly hybrid and hierarchical design of compute clusters and high-end supercomputers, as well as the use of accelerator components (Cell BE or GPGPUs, e.g.) add further challenges to efficient programming in HPC applications.
Therefore, compute and data intensive tasks can only benefit from the hardware’s full potential, if both processor and architecture features are taken into account at all stages ? from the early algorithmic design to the final implementation.
The AASC workshop strives to address all aspects related to these issues, including, but not limited to:
Hardware-aware, compute- and memory-intensive simulations of real-world problems in computational science and engineering (for example, from applications in electrical, mechanical, civil, or medical engineering).
Architecture-aware approaches for large-scale parallel simulations in both implementation and algorithm design, including scalability studies.
Architecture-aware parallelisation on HPC platforms; esp. platforms with hierarchical communication layout, multi-/many-core platforms, NUMA architectures, or accelerator components (Cell BE, GPU, FPGA).
Parallelisation with appropriate programming models and tool support for multi-core and hybrid platforms.
Software engineering, code optimisation, and code generation strategies for parallel systems with multi-core processors.
Tools for performance and cache behavior analysis (including cache simulation) for parallel systems with multi-core processors.