DRNoC 2015 - International Workshop on Dynamic Reconfigurable Network-on-Chip (DRNoC 2015)

Emerging SoCs (System-on-Chip, such as those for mobile systems, are typically battery-powered systems and have to support a wide range of streaming applications such as video and audio. Network-on-chip has been recently proposed for SoCs applications design to achieve better performance and lower energy consumption when compared to conventional on-chip bus architectures.
Several approaches have been proposed to deal with NoCs and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored an application domain or a specific application by providing an application- specific NoC. All parameters, such as the on-chip interconnect architecture (i.e., topology), routing, and switching schemes, are defined at design time. However, NoC should be scalable and adaptive to support various applications by selecting the most suitable parameters based on the requirements of the current application and system conditions.
Recently, there has been a great deal of interest in the development of run-time approaches for reconfigurable NoCs. These approaches provide techniques that allow NoCs to autonomously adapt its structure and their behavior during the course of their operation (i.e., in runtime). For example, the number of VCs (virtual channels) and the buffer size per VC can be dynamically adjusted based on the traffic load and network status.
DRNoC 2015 workshop is intended to serve as a forum and bring together the researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of dynamic reconfigurable NoCs. It will cover current and new approaches and relevant activities in the design, analysis, and evaluation of techniques for dynamic reconfigurable NoCs.
The DRNoC Workshop topics of interest include (but are not limited to) the following:
Topologies reconfiguration for NoCs
Routing algorithms, switching techniques, and flow control schemes
Mapping and scheduling of tasks into NoCs
Self-reconfiguration and self-optimization of NoCs
Bio-inspired techniques for reconfigurable NoCs
Analytical evaluation methods for designing reconfigurable NoCs
Area, energy, and performance evaluation
Tools for design space exploration of reconfigurable NoCs
Cases studies and FPGA-based implementation of reconfigurable NoCs