DataFlow 2014 - Symposia on Data Flow Algorithms and Architecture for Signal Processing Systems

This symposium addresses timely and challenging problems in the design and implementation of dataflow-based techniques for signal processing systems, driven by the increase in complexity of signal processing applications, the demanding constraints of these applications, and the large diversity of relevant processing platforms, including platforms based on field programmable gate arrays (FPGAs), graphics processing units (GPUs), programmable digital signal processors (PDSPs), and various forms of application-specific processors. This symposium will provide a platform for the dissemination of research on topics of interest but not limited to the following:
Dataflow architectures
Accelerator architectures for DSP
Dataflow-based modeling and analysis
Methods for assessing and optimizing the productivity, retargetability, and reliability provided by dataflow-based methodologies.
Tools for optimized synthesis of hardware and software from high level, dataflow-based application specifications.
Advanced dataflow methodologies and architectures that are specialized to specific signal processing application domains, such as biomedical signal processing, cognitive radio, cryptography, compression, multimedia processing, and video coding, and dataflow algorithms in these areas.
Keynote Speakers
Prof. Shuvra S. Bhattacharyya, University of Maryland, College Park, USA, “Dataflow Scheduling Techniques for Multicore Digital Signal Processors”.
Dr. Lee Barford, Agilent Technologies, USA, “Data flow algorithms for processors with vector extensions”
Dr. Jacob Kornerup, National Instruments, USA, “From Algorithm to Hardware using Data Flow”
Organizers
General Chairs:
Warren Gross, McGill University, Canada
Jorn Janneck, Lund University, Sweden
Technical Program Chairs:
Joseph Cavallaro, Rice University, USA
Zhiyuan Yan, Lehigh University, USA
TPC Members
Neal Bambha, US Army Research Lab USA
Jani Boutellier, University of Oulu Finland
Peter Cappello, University of California, Santa Barbara USA
Ching-Te Chiu, National Tsing Hua University Taiwan
Brian Evans, University of Texas at Austin USA
Christophe Jego, IPB/ENSEIRB-MATMECA France
Izzet Kale, University of Westminster UK
Jacob Kornerup, National Instruments USA
Marco Mattavelli, EPFL Switzerland
John McAllister, Queen's University Belfast UK
Peter Milder, Stony Brook University USA
Stephen Neuendorffer, Xilinx USA
Sridhar Rajagopal, Samsung USA
Sriram Sundararajan, Broadcom, Inc. USA
Wonyong Sung, Seoul National University Korea
Lei Wang, University of Connecticut USA
Xinmiao Zhang, xxz36-AT-case.edu Sandisk USA
Zheng Zhou, Texas Instruments USA
Jun Zhu
Contacts
For all inquiries and questions please contact Dr. Joseph Cavallaro at cavallar-AT-rice.edu