ICMTS 2011 - International Conference on Microelectronic Test Structures ICMTS 2011

The IEEE Electron Devices Society sponsors the 24th International Conference on Microelectronic Test Structures to be held in downtown Amsterdam at the Royal Academy of Arts and Sciences. The purpose is to bring together designers and users of test structures to discuss recent developments and future directions. The conference will be held on April 5-7, 2011, and will be preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on April 4. There will also be an equipment exhibition relating to test structure measurements. Original papers are solicited presenting new developments in test structures related to microelectronic, nanotechnology and MEMS research. This includes their implementation, and applications as well as test structures aimed at the characterisation of new materials and devices. A Best Paper award will be presented by the Technical Program Committee. A selection of contributed papers will appear in a special issue of IEEE Transactions on Semiconductor Manufacturing. Suggested topics include (but are not limited to):
Material and Process Characterisation: Wafer start material evaluation, SiGe, strained silicon, Silicon-On-Insulator, Ge, GaAs, GaN and other compounds, homoepitaxial and heteroepitaxial layers. Resistivity, mobility, stress, contact resistance, dielectric, and interconnect measurements.
Test structure design methods: Design flows for automated design, verification strategies, design for analysis (methods to extract CA, number of squares, density, via/contact counts), parametrized design, design issues (grid, hierarchy, floating point issues, misalignment).
Replicated Feature Metrology: Level-to-Level registration, overlay, CD uniformity and control, non-electrical characterisation techniques, MOS effective gate length/width evaluation, mask and reticle process control.
Manufacturing of Integrated Circuits and MEMS: Evaluation of individual and groups of integrated circuit, device and MEMS process steps and elements: transistors, diodes, mechanical structures, device isolation, memory cells, and interconnect. Assessment of MMICs and RF components and products. Evaluation and optimisation of standard cell macros and other product circuits.
Reliability and Product Failure Analysis: Test structures for quality assurance, transistor, thin film, dielectric and interconnect reliability, thermal monitoring and analysis, accelerated wafer level tests, wafer level burn-in, failure identification, reliability prediction.
Nanotechnology, Displays and Emerging Devices: Test structures and methods to evaluate nanotechnology (materials and devices), displays, optoelectronic materials and new devices.
MEMS, Sensors and Actuators: Test structures for MEMS and micromachining including physical/chemical/optical sensors, photonic devices, image sensors and bio-sensors, amorphous silicon films and devices
Device and Circuit Modelling, Parameter Extraction: Model parameter extraction, RF device modelling, de-embedding, pulsed measurements, DC and high frequency measurement techniques and applications.
Technology R&D and Integration: Test structures for FEOL or BEOL evaluation, design rule determination, process uniformity and worst-case analysis, test structures to assess integration and new technologies, multiplexed test chips/devices for large scale evaluations / reduced pad count.
Yield Enhancement, and Production Process Control: Yield enhancement structures and methods, critical area calculation, defect estimation structures and methods, yield modelling, evaluation of design-manufacturing interactions (Design for Yield), place and route methodology, Statistical Process Control. Large-scale, many-component test circuitry for technology assessment e.g. arrays, multiplexing techniques.
Test Structure Measurement Utilisation Strategy: Test equipment, probing and programmable testing for process diagnostics, optimizing test throughput, database and data analysis methods, statistical data analysis, expert systems and related techniques. Amongst others this includes capacitance, voltage, current, resistance, optical and thermal measurements.
Matching Test Structures: Matching (or variability) of components (transistors, resistors, capacitors, inductors) ? layout for circuit applications and their evaluation. Characterisation of identically designed components. Matching models.
Authors are asked to submit an extended abstract of up four pages in PDF format (font-embedded). The first page must consist of a title, a 50-words summary, author’s name, the full address, fax number and e-mail address of the lead author, and author preference for oral or poster session presentation if any. The body of the abstract should be a max of three pages consisting of the text, major figures and tables, data for review and references. Please ensure all figures are of a size that makes them legible. The WWW page for paper submission can be accessed through the ICMTS official web page: http://www.eng.ed.ac.uk/ICMTS/ .
The selection process will be based on the technical merit and will be highly weighted in favour of papers that have high test structure content and include measurement data, analysis, and illustrations of the test structures involved. The title page and extended abstracts received by September 17, 2010 will be considered for the conference. A notice of paper acceptance with instructions for manuscript preparation for the conference proceedings will be sent to authors of papers selected for presentation by November 1, 2010. Final papers will be required by January 14, 2011.
For further technical information contact Prof. Dr. Luca Selmi
Università degli Studi di Udine
luca.selmi-AT-uniud.it