CARL 2013 - Workshop on Intersections of Computer Architecture and Reconfigurable Logic
Topics/Call fo Papers
The Third Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013)
Davis, California - Saturday, December 7, 2013
Co-located with MICRO-46
http://www.ece.cmu.edu/calcm/carl
The Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL) is a new forum for presenting FPGA and reconfigurable logic research relevant to a computer architecture audience. In recent years, there has been a renewed interest in reconfigurable computing, driven by the need for greater computing performance and, at the same time, better power and energy efficiency. Reconfigurable computing is a key technology candidate to efficiently leverage exponential device scaling beyond current multicore processors.
This full-day workshop will be held on Saturday, December 7, 2013, co-located with MICRO-46 in Davis, CA.
Call for Papers
Research Papers. We invite research papers from all areas of FPGA and reconfigurable logic that impact the computer architecture community. Major areas of interests include, but are not limited to:
New FPGA architectures and reconfigurable fabric designed to support computing
Heterogeneous computing processors and systems that incorporate reconfigurable logic
Computation models and programming tools for reconfigurable and heterogeneous computing
State-of-the-art (ready-for-use) reconfigurable computing platforms and infrastructure
Algorithms and applications for reconfigurable computing (including FPGA-based prototyping and simulation of computer systems)
Evaluations of reconfigurable computing in terms of performance, power/energy, flexibility and cost, especially in comparison to other hardware paradigms (multicore, GPU, ASICs, etc.).
We will accept submissions in two categories: (1) new unpublished manuscripts (okay if under review by a conference of a later date), and (2) audience-appropriate revisions of papers already published outside of traditional computer architecture forums (ISCA, MICRO, HPCA, PACT, etc.). Papers selected for presentations will not be published in any formal proceedings.
A submission should be 4~6 pages in double-column format. The review process is not blind; please include authors' names and affiliations. Please clearly indicate whether a submission is category 1 or 2 in the header area of the submission. If category 2, the source materials must be explicitly introduced in both the abstract and introduction.
Questions? Please email questions about this Call-for-Papers to jhoe-AT-ece.cmu.edu.
Davis, California - Saturday, December 7, 2013
Co-located with MICRO-46
http://www.ece.cmu.edu/calcm/carl
The Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL) is a new forum for presenting FPGA and reconfigurable logic research relevant to a computer architecture audience. In recent years, there has been a renewed interest in reconfigurable computing, driven by the need for greater computing performance and, at the same time, better power and energy efficiency. Reconfigurable computing is a key technology candidate to efficiently leverage exponential device scaling beyond current multicore processors.
This full-day workshop will be held on Saturday, December 7, 2013, co-located with MICRO-46 in Davis, CA.
Call for Papers
Research Papers. We invite research papers from all areas of FPGA and reconfigurable logic that impact the computer architecture community. Major areas of interests include, but are not limited to:
New FPGA architectures and reconfigurable fabric designed to support computing
Heterogeneous computing processors and systems that incorporate reconfigurable logic
Computation models and programming tools for reconfigurable and heterogeneous computing
State-of-the-art (ready-for-use) reconfigurable computing platforms and infrastructure
Algorithms and applications for reconfigurable computing (including FPGA-based prototyping and simulation of computer systems)
Evaluations of reconfigurable computing in terms of performance, power/energy, flexibility and cost, especially in comparison to other hardware paradigms (multicore, GPU, ASICs, etc.).
We will accept submissions in two categories: (1) new unpublished manuscripts (okay if under review by a conference of a later date), and (2) audience-appropriate revisions of papers already published outside of traditional computer architecture forums (ISCA, MICRO, HPCA, PACT, etc.). Papers selected for presentations will not be published in any formal proceedings.
A submission should be 4~6 pages in double-column format. The review process is not blind; please include authors' names and affiliations. Please clearly indicate whether a submission is category 1 or 2 in the header area of the submission. If category 2, the source materials must be explicitly introduced in both the abstract and introduction.
Questions? Please email questions about this Call-for-Papers to jhoe-AT-ece.cmu.edu.
Other CFPs
Last modified: 2013-09-20 06:15:36