SDD 2012 - 2012 8th IEEE International Workshop on Silicon Debug and Diagnosis (SDD)

Troubleshooting how and why systems and circuits fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, correcting the design function, failure mode learning for R&D, or just getting a working first prototype. This detective work is however very tricky. Sources of difficulty include circuit and system complexity, packaging, limited physical access, shortened product creation cycle and time-to-market. New and efficient solutions for debug and diagnosis have a much needed and highly visible impact on productivity.
SDD 2012 will be held in Anaheim, California, USA. It is the eighth of a series of highly successful technical workshops that consider issues related to debug & diagnosis of semiconductor circuits and systems - from prototype bring-up to volume production.
The topics of interest include, but are not limited to, the following:
Debug Techniques and Methodologies Microprocessor, FPGA, IP, SOC Debug
Design and Debug Infrastructure IP for SDD
DFT Reuse for Debug and Diagnosis System Level Debug & Diagnosis
Manufacturing & Prototype Environment Emulation & Hardware Acceleration
Debug Standardization Linking Pre-Silicon Verification to Post-Silicon Validation
Case Studies SDD vs. Yield & TTM
3D Stacked IC Debug Silicon Debug & Diagnosis Tools and Automation
Author Information
The workshop objective is to facilitate an interactive information exchange. Extended abstracts and papers may be short. Proposals that describe open issues, industry/technology needs or opinions are valuable to the program. The SDD 2012 workshop does not have a formal proceedings, however an informal digest of papers will be distributed to the workshop participants. Furthermore, the authors of the best contributions to the SDD 2012 workshop will be invited by the program and general chair to submit an extended version of their work to a special section on Silicon Debug and Diagnosis to be published by IEEE Design & Test of Computers in Summer 2013.
Length Guideline: ranging from a one page, extended abstract up to 8 pages.
Submissions due: September 7th, 2012
Acceptance Notification: September 29th, 2012
Final versions: October 22nd, 2012