3D-Test 2012 - 2012 Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test)

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.
Topic Areas - You are invited to participate and submit your contributions to the 3D-TEST Workshop. The workshop's areas of interest include (but are not limited to) the following topics:
Defects due to Wafer Thinning
Defects in Intra-Stack Interconnects
DfT Architectures for 3D-SICs
EDA Design-to-Test Flow for 3D-SICs
Failure Analysis for 3D-SICs
Known-Good Die / Stack Testing
Pre-Bond and Post-Bond Testing
Reliability of 3D-SICs
Standardization for 3D Testing
System/Board Test Issues for 3D-SICs
Test Cost Modeling for 3D-SICs
Test Flow Optimization for 3D-SICs
Tester Architecture incl. ATE and BIST
Thermal/Mechanical Stress in 3D-SICs
TSV Test, Redundancy, and Repair
Wafer Probing and Probe Damage of 3D-SICs
Submission Instructions - Submission of papers in closed now. However, it is still possible to submit proposals for poster presentation. Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows (Extended) Abstract submissions. Detailed submission instructions can be found at the Workshop's website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop. Selected submissions can at this point only be accepted for poster presentation at the Workshop.
Publications - The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc. Authors of a selected subset of submissions will be invited to submit an extended and re-worked version of their manuscript to be considered for publication in IEEE ‘Design & Test of Computers'.