DRNoC 2012 - International Workshop on Dynamic Reconfigurable Network-on-Chip (DRNoC 2012)

SCOPE AND OBJECTIVES
Emerging SoCs (System-on-Chip, such as those for mobile systems, are typically battery-powered systems and have to support a wide range of streaming applications such as video and audio. Network-on-chip has been recently proposed for SoCs applications design to achieve better performance and lower energy consumption when compared to conventional on-chip bus architectures.
Several approaches have been proposed to deal with NoCs and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored an application domain or a specific application by providing an application- specific NoC. All parameters, such as the on-chip interconnect architecture (i.e., topology), routing, and switching schemes, are defined at design time. However, NoC should be scalable and adaptive to support various applications by selecting the most suitable parameters based on the requirements of the current application and system conditions.
Recently, there has been a great deal of interest in the development of run-time approaches for reconfigurable NoCs. These approaches provide techniques that allow NoCs to autonomously adapt its structure and their behavior during the course of their operation (i.e., in runtime). For example, the number of VCs (virtual channels) and the buffer size per VC can be dynamically adjusted based on the traffic load and network status.
DRNoC’12 workshop is intended to serve as a forum and bring together the researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of dynamic reconfigurable NoCs. It will cover current and new approaches and relevant activities in the design, analysis, and evaluation of techniques for dynamic reconfigurable NoCs.
The Workshop topics of interest include (but are not limited to) the following:
Topologies reconfiguration for NoCs
Routing algorithms, switching techniques, and flow control schemes
Mapping and scheduling of tasks into NoCs
Self-reconfiguration and self-optimization of NoCs
Bio-inspired techniques for reconfigurable NoCs
Analytical evaluation methods for designing reconfigurable NoCs
Area, energy, and performance evaluation
Tools for design space exploration of reconfigurable NoCs
Cases studies and FPGA-based implementation of reconfigurable NoCs
INSTRUCTIONS FOR AUTHORS:
You are invited to submit original and unpublished research works on above and other topics related to Dynamic Reconfigurable Network-on-Chip. Submitted papers must not have been published or simultaneously submitted elsewhere. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and email addresses. Please, indicate clearly the corresponding author and include up to 6 keywords from the above list of topics and an abstract of no more than 400 words. The full manuscript should be at most 7 pages using the two-column IEEE format. Additional pages will be charged additional fee. Short papers (up to 4 pages), poster papers and posters (please refer to http://hpcs2012.cisedu.info/home/posters for the submission details) will also be accepted for submission. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments.
Submit a PDF copy of your full manuscript via email to the Workshop organizers at mohamed.bakhouya-AT-aalto.fi and jaafar.gaber-AT-utbm.fr.
Only PDF files will be accepted, sent by email to the workshop organizers. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, technical clarity and presentation. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. Authors of accepted papers must guarantee that their papers will be registered and presented at the workshop.
Accepted papers will be published in the Conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2012 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE Digital Library and indexed accordingly.
If you have any questions about paper submission or the workshop, please contact the workshop organizers.
IMPORTANT DATES
Abstract submission: February 22, 2012
Paper Submissions: February 28, 2012
Acceptance Notification: March 21, 2012
Camera Ready Papers and Registration Due: April 17, 2012
Conference Dates: July 2 ? 6, 2012