HEART 2011 - International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies
Date2011-06-02
Deadline2011-02-15
VenueImperial C, UK - United Kingdom
KeywordsHigh performance computing; Power performance; CAD tools; GPU; FPGA; Other devices
Websitehttp://www.isheart.org
Topics/Call fo Papers
The 2nd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:
In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.
- Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA, GPU, CELL/B.E and other devices
- Heterogeneous processors/systems for scalable, high-performance, high-reliability and/or low-power computation
- Reconfigurable/configurable hardware and systems including IP-cores, embedded systems, SoCs and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
- High-performance custom-computing processors/systems
- Novel architectures and device technologies that can be applied to efficient acceleration, including many-core architectures, NoC architectures, 3D-stacking technologies and optical devices
- Software and applications:
- Novel applications for efficient acceleration systems/platforms, and custom computing
- Compiler techniques and programming languages for efficient acceleration systems/platforms, including many-core processors, GPUs, FPGAs and other reconfigurable/custom processors
- Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems
In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.
- Paper submission:??February 15, 2011
- Author notification:??April 1, 2011
- Camera-ready deadline:??April 15, 2011
- Workshop Dates:??June 2-3, 2011
Other CFPs
Last modified: 2011-01-11 08:36:09