AFFORD 2018 - Workshop on Practical Formal Verification for Software Dependability (AFFORD 2018)
Date2018-10-15 - 2018-10-18
Deadline2018-07-15
VenueMemphis, TN, USA - United States
Keywords
Websitehttps://2018.issre.net
Topics/Call fo Papers
For a large majority of software engineers and developers, formal verification techniques are seen rather as expert tools and not as engineering tools that can be used on a daily basis. This is mostly the case in the context of main stream systems (e.g. automotive, medical, industrial automation) where pragmatics (e.g. personnel skills, cost structures, deadlines, existent processes, existent organization, legacy code) plays a major role.
This workshop aims to build a cohesive community interested in the application of formal verification techniques to increase dependability of software intensive systems, by developing and promoting approaches, techniques and tools that can be understood and applied by practicing engineers – without special education in formal methods. Specifically, we aim to bring together researchers and practitioners interested in lowering the adoption barrier to use formal verification for the development of dependable software. We especially focus on the needs of main stream developers that do not (necessarily) work on highly safety critical systems but on more main stream systems that still need to be dependable.
Topics of interests include but are not limited to:
increase software dependability by using formal verification
lowering the adoption barrier of formal verification by practicing engineers
using formal verification results as evidence for certification
complementing formal verification with reviews and tests
measuring the confidence gained even when incomplete or unsound verification is used
process-phase specific formal verification techniques: from requirements engineering to deployment and software maintenance
integrating formal verification with agile development
using formal verification in the development of low criticality systems
domain specific formal verification (e.g. embedded systems, web applications)
use of ”invisible” formal techniques like type-systems
evaluate and increase the usability of formal verification tooling (e.g. specification of verification conditions, interpretation of verification results, specification of the environment)
using domain specific languages and model based development to improve the usability of verification
tools that provide a high degree of automation
integration of formal techniques in development environments
industrial experiences with using formal verification in contexts as described above
experience about failures to apply suitable verification in an industrial context
This workshop aims to build a cohesive community interested in the application of formal verification techniques to increase dependability of software intensive systems, by developing and promoting approaches, techniques and tools that can be understood and applied by practicing engineers – without special education in formal methods. Specifically, we aim to bring together researchers and practitioners interested in lowering the adoption barrier to use formal verification for the development of dependable software. We especially focus on the needs of main stream developers that do not (necessarily) work on highly safety critical systems but on more main stream systems that still need to be dependable.
Topics of interests include but are not limited to:
increase software dependability by using formal verification
lowering the adoption barrier of formal verification by practicing engineers
using formal verification results as evidence for certification
complementing formal verification with reviews and tests
measuring the confidence gained even when incomplete or unsound verification is used
process-phase specific formal verification techniques: from requirements engineering to deployment and software maintenance
integrating formal verification with agile development
using formal verification in the development of low criticality systems
domain specific formal verification (e.g. embedded systems, web applications)
use of ”invisible” formal techniques like type-systems
evaluate and increase the usability of formal verification tooling (e.g. specification of verification conditions, interpretation of verification results, specification of the environment)
using domain specific languages and model based development to improve the usability of verification
tools that provide a high degree of automation
integration of formal techniques in development environments
industrial experiences with using formal verification in contexts as described above
experience about failures to apply suitable verification in an industrial context
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Last modified: 2018-06-29 15:36:28