P^3MA 2018 - 3rd International Workshop on Performance Portable Programming Models for Accelerators (P^3MA)
Topics/Call fo Papers
As the HPC community approaches exascale platforms, heterogeneity in compute and memory hierarchies is in most cases either remaining or increasing in complexity. High-level programming models aim to provide scientific applications a solution to maintain expected performance on diversifying systems with a minimal loss of portability or programmer productivity. Directives represent a traditional approach to high-level portability abstractions, with other successful strategies including Domain Specific Languages (DSLs), C++ metaprogramming, and runtime APIs. Although these approaches attempt to introduce abstraction without performance penalty, challenges remain with their designs, implementations, and ease-of-use on rapidly evolving hardware and diverse memory subsystems.
Programming methods to address these concerns are continuously being developed within standards committees for C++, OpenCL, OpenMP, OpenACC, and various DSLs. This workshop is designed to assess improved features of programming models designed for performance portability and productivity on heterogeneous systems, their implementations, and experiences with their deployment in HPC applications.
As in the past years, this workshop will provide a forum to bring together researchers and developers to examine heterogeneous computing and how it has been evolving across an increasingly diverse set of accelerated architectures.
Topics of interest for workshop submissions include (but are not limited to):
• Experience porting applications using high-level models focused on performance portability and productivity
• Hybrid heterogeneous or many-core programming with models such as threading, message passing, and PGAS
• Continuation-style and asynchronous task-based programming
• Scientific libraries designed for performance portability on heterogeneous systems
• Experiences in implementing compilers for performance portable programming on current and emerging architectures
• Low level communications APIs or runtimes that support accelerator architectures
• Extensions to programming models needed to support multiple memory hierarchies and accelerators
• Performance modeling and evaluation tools
• Power/energy studies
• Auto-tuning or optimization strategies
• Benchmarks and validation suites
Important Deadlines:
April 03, 2018: Paper submission deadline
May 14, 2018: Paper acceptance notification
June 03, 2018: Camera ready paper
June 28, 2018: Workshop
Papers submission guidelines:
Abstracts and papers need to be submitted via Easy Chair: https://easychair.org/conferences/?conf=p3ma0
After the reviewing process, the accepted papers will be published in the [Springer-Verlag Lecture Notes in Computer Science (LNCS)](http://www.springer.com/us/computer-science/lncs) volumes.
We only accept paper submissions which are formatted correctly in [LNCS style]
(http://www.springer.com/us/computer-science/lncs/c...) (single column format) using either the LaTeX document class or Word template. For details on the author guidelines, please refer to Springer's website. Incorrectly formatted papers will be excluded from the reviewing process.
Papers submissions are required to be within 18 pages in the above mentioned LNCS style. This includes all figures and references.
Review process:
All submitted manuscripts will be reviewed. The review process is not double blind, i.e., authors will be known to reviewers. All submitted manuscripts will be reviewed. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the conference scope. Submitted papers may NOT have appeared in or be under consideration for another conference, workshop or journal.
COMMITTEES
Steering Committee
Matthias Muller, RWTH Aachen University, Germany
Barbara Chapman, Stony Brook University, USA
Oscar Hernandez, ORNL, USA
Duncan Poole, OpenACC,
Torsten Hoefler, ETH, Zurich
Michael Wong, Codeplay Software Ltd, Canada
Mitsuhisa Sato, University of Tsukuba, Japan
Michael Klemm, OpenMP
Kuan-Ching Li, Providence University, Taiwan
Program Chairs
Sunita Chandrasekaran, University of Delaware, USA
Graham Lopez, ORNL, USA
Program Committee
Cheng Wang, Microsoft, USA
Sandra Wienke, RTWH Aachen, Germany
Robert Herschel, U. Indiana, USA
Swaroop Pophale, ORNL, USA
Samuel Thibault, INRIA, University of Bordeaux, France
James Beyer, NVIDIA, USA
Wei Ding, NVIDIA, USA
Adrian Jackson, University of Edinburgh, Scotland
Guido Juckeland, HZDR, Germany
Suraj Prabhakaran, Intel, Germany
Sameer Shende, U. Oregon, USA
Daniel Tian, PGI, USA
Programming methods to address these concerns are continuously being developed within standards committees for C++, OpenCL, OpenMP, OpenACC, and various DSLs. This workshop is designed to assess improved features of programming models designed for performance portability and productivity on heterogeneous systems, their implementations, and experiences with their deployment in HPC applications.
As in the past years, this workshop will provide a forum to bring together researchers and developers to examine heterogeneous computing and how it has been evolving across an increasingly diverse set of accelerated architectures.
Topics of interest for workshop submissions include (but are not limited to):
• Experience porting applications using high-level models focused on performance portability and productivity
• Hybrid heterogeneous or many-core programming with models such as threading, message passing, and PGAS
• Continuation-style and asynchronous task-based programming
• Scientific libraries designed for performance portability on heterogeneous systems
• Experiences in implementing compilers for performance portable programming on current and emerging architectures
• Low level communications APIs or runtimes that support accelerator architectures
• Extensions to programming models needed to support multiple memory hierarchies and accelerators
• Performance modeling and evaluation tools
• Power/energy studies
• Auto-tuning or optimization strategies
• Benchmarks and validation suites
Important Deadlines:
April 03, 2018: Paper submission deadline
May 14, 2018: Paper acceptance notification
June 03, 2018: Camera ready paper
June 28, 2018: Workshop
Papers submission guidelines:
Abstracts and papers need to be submitted via Easy Chair: https://easychair.org/conferences/?conf=p3ma0
After the reviewing process, the accepted papers will be published in the [Springer-Verlag Lecture Notes in Computer Science (LNCS)](http://www.springer.com/us/computer-science/lncs) volumes.
We only accept paper submissions which are formatted correctly in [LNCS style]
(http://www.springer.com/us/computer-science/lncs/c...) (single column format) using either the LaTeX document class or Word template. For details on the author guidelines, please refer to Springer's website. Incorrectly formatted papers will be excluded from the reviewing process.
Papers submissions are required to be within 18 pages in the above mentioned LNCS style. This includes all figures and references.
Review process:
All submitted manuscripts will be reviewed. The review process is not double blind, i.e., authors will be known to reviewers. All submitted manuscripts will be reviewed. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the conference scope. Submitted papers may NOT have appeared in or be under consideration for another conference, workshop or journal.
COMMITTEES
Steering Committee
Matthias Muller, RWTH Aachen University, Germany
Barbara Chapman, Stony Brook University, USA
Oscar Hernandez, ORNL, USA
Duncan Poole, OpenACC,
Torsten Hoefler, ETH, Zurich
Michael Wong, Codeplay Software Ltd, Canada
Mitsuhisa Sato, University of Tsukuba, Japan
Michael Klemm, OpenMP
Kuan-Ching Li, Providence University, Taiwan
Program Chairs
Sunita Chandrasekaran, University of Delaware, USA
Graham Lopez, ORNL, USA
Program Committee
Cheng Wang, Microsoft, USA
Sandra Wienke, RTWH Aachen, Germany
Robert Herschel, U. Indiana, USA
Swaroop Pophale, ORNL, USA
Samuel Thibault, INRIA, University of Bordeaux, France
James Beyer, NVIDIA, USA
Wei Ding, NVIDIA, USA
Adrian Jackson, University of Edinburgh, Scotland
Guido Juckeland, HZDR, Germany
Suraj Prabhakaran, Intel, Germany
Sameer Shende, U. Oregon, USA
Daniel Tian, PGI, USA
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Last modified: 2018-02-16 15:25:55