DPNoC 2017 - 4th International Workshop on Design and Performance of Networks on Chip (DPNoC 2017)

The advance in silicon technology has led to the emergence of on-Chip Systems (SoC), where a complete system with a large number of intellectual property cores can be integrated onto a single silicon chip. The performance of SoCs highly depends on the speed and efficiency of their underlying communications subsystems. The light weight networks, known as Network-on-Chip (NoC), have been introduced to overcome the scalability problem found in shared-bus communication architectures. Intensive research studies have been undertaken investigating the design cost, in terms of silicon area and power consumption, and performance of NoC. Most of these studies are targeting NoC topology, router microarchitecture, switching techniques, routing algorithms, and application mapping onto NoC.
The workshop on the Design and Performance of Networks on Chip (DPNoC'2016) will represent an international forum for researchers from both academia and industry to expose the latest trends, research findings, and emerging issues in this area.
The Workshop topics include (but are not limited to) the following:
Technology constraints on NoCs
Router microarchitecture
Flow control techniques
Switching techniques
Routing protocols
Fault tolerance/reliability in NoC
Technology constraints on NoCs
Scheduling and application mapping onto NoC
Wireless NoCs
NOCs modeling and performance evaluation
NOC scalability
FPGA-based implementation of reconfigurable NoCs
Journal Special Issue
Extended version of all accepted papers in the workshop will be published as special issue on The International Journal of Computing and Digital Systems (IJCDS)