RAW 2011 - The 18th Reconfigurable Architectures Workshop (RAW 2011)

The 18th Reconfigurable Architectures Workshop (RAW 2011) will be held in Anchorage, Alaska, USA in May 2011. RAW 2011 is associated with the 25th Annual International Parallel & Distributed Processing Symposium (IPDPS 2011) and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.
Run-Time Reconfiguration & Adaptive Computing:
Architectures, Algorithms, Technologies
Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse-/multi-grain devices) appear to have more room for exploiting run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2011 aims to provide a forum for creative and productive interaction between all these disciplines.
Topics of Interest
Authors are invited to submit manuscripts of original unpublished research in all areas of dynamic and run-time reconfiguration (foundations, algorithms, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and applications). The topics of interest include, but are not limited to:

Models & Architectures
? Theoretical Interconnect
and Computation Models
? RTR Models and Systems
? RTR Hardware Architectures
? Optical Interconnect Models
? Simulation and Prototyping
? Bounds and Complexity Issues
Algorithms & Applications
? Algorithmic Techniques
? Mapping Parallel Algorithms
? Distributed Systems & Networks
? Fault Tolerance Issues
? Wireless and Mobile Systems
? Automotive Applications
? Infotainment & Multimedia
? Biology Inspired Applications
Design, Technologies & Tools
? Configurable Systems-on-Chip
? Energy Efficiency Issues
? Devices and Circuits
? Reconfiguration Techniques
? High Level Design Methods
? System Support
? Adaptive Runtime Systems
? Organic Computing
Important Dates:
Submission deadline: October 18, 2010
Notification of acceptance: December, 2010
Camera-ready papers due: February, 2011