TAU 2017 - ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

The TAU series of workshops provide an informal forum for practitioners and researchers working on these and other temporal aspects of analog and digital systems to disseminate early work and engage in a free discussion of ideas. The twenty-third in the TAU series, the TAU 2017 workshop invites submissions and proposals from the traditional as well as emerging areas related to the timing properties of digital electronic systems, including but not limited to the topics listed below.
- Timing: System/circuit/gate/transistor-level timing, FPGAs, New latches, dual-edge devices, distributed timing
- Modeling and simulation: Digital, analog, mixed-signal circuits, Aging and reliability
- Variability: Modeling and analysis
- Power, trade-offs and optimization
- Signal integrity
- Clocking
- Characterization: Library (cell/latch/SRAM) characterization
- Hierarchical timing: Timing macro-modeling
- Emerging technologies: Full custom design analysis, sensor placement, 3D ICs, TSVs
- Others: Integrated functional-temporal analysis, formal methods, asynchronous systems