ReConFig 2016 - 2016 International Conference on ReConFigurable Computing and FPGA's

2016 International Conference on ReConFigurable Computing and FPGA's
Nov 30 - Dec 2, 2016, Cancun, Mexico.
* 3 Keynote Speeches
* Technical Sessions (General Sessions + 9 Special Tracks)
* PhD Forum
* Demo Night
* Social Events
IEEE CASS Technical Cosponsorship.
Conference Proceedings by the IEEE, to be included in IEEE Digital
library (IEEE Xplore). Special Issues of International Journals.
Deadline for Submissions: July 15, 2016
***
Call for Papers
It is our pleasure to invite you to participate in the 2016
International Conference on Reconfigurable Computing and FPGAs
(ReConFig ’16). The eleventh ReConFig will be held in Cancun, Mexico,
during November 30 - December 2, 2016.
Reconfigurable computing and FPGA technology have become major subjects
of research in computing and electrical engineering as they have been
identified as powerful alternatives for creating highly efficient
computing systems. Reconfigurable computing offers substantial
performance improvements when compared against traditional processing
architectures via custom design and reconfiguration capabilities.
Reconfiguration is characterized by the ability of hardware
architectures or devices to rapidly alter the functionalities of its
components and the interconnection between them as needed. Existing
theoretical models and algorithms combined with commercially available
devices, such as FPGAs, make Reconfigurable Computing a very powerful
computing paradigm.
Topics
ReConFig is one of the leading forums in the field that brings together
an appropriate mix of all theoretical and practical aspects of
reconfigurable computing and FPGA technology. The conference promotes
the use of reconfigurable computing and FPGAs devices for research,
education, and applications, covering from hardware architectures and
devices to custom computers and high performance systems.
ReConFig covers a broad spectrum of topics including, but not limited
to:
* Models, methods, tools, and architectures for reconfigurable computing
* Compilation, simulation, debugging, synthesis, verification, and test
of reconfigurable systems
* Field programmable gate arrays and other reconfigurable technologies
* Evolvable hardware and dynamic reconfiguration
* Algorithms implemented on reconfigurable hardware
* Reconfigurable computing education
* Reconfigurable computing applications
In addition to the general session, submissions are invited for the
following tracks:
* High Performance Reconfigurable Computing
* Productivity Environments and High Level Languages
* Reconfiguration Techniques
* Reconfigurable Computing for Security and Cryptography
* Reconfigurable Computing for Networks and Communications
* Reconfigurable Computing in Space
* Reconfigurable Computing with GPUs and APUs
* Reconfigurable Computing for Signal Processing
* Multiprocessor Systems and Networks on Chip
* Phd Forum
Demo Night
All attendees will be encouraged to bring their hardware/software for
display at the ReConFig 2016 Demo Night.
Conference Proceedings
Conference Proceedings will be edited by the IEEE and will appear at
IEEE Xplore Digital Library. Authors of selected papers will be invited
to submit an extended version for a ReConFig’16 Special Issue of
International Journals (TBA).
Submission information
Regular submissions should be no more than 6 pages long including
tables, figures and references. They have to be submitted for
evaluation as a PDF file using IEEE formatting.
Important Dates
Full Paper Submission: July 15, 2016
Acceptance Notification: September 16, 2016
Final paper submission: October 0, 2016
Conference: November 30 - December 2, 2016
Organizing Committee
General Chair
René Cumplido, INAOE, Mexico
Program co-Chairs
Peter Athanas, Virginia Tech, USA
Ron Sass, UNC-Charlotte, USA
Proceedings Chair
Claudia Feregrino, INAOE, Mexico
Publicity Chair
Alicia Morales, INAOE, Mexico
Tracks co-Chairs
Hugo Andrade, National Instruments, USA
David Andrews, University of Arkansas, USA
Jason Bakos, University of South Carolina, USA
Gordon Brebner, Xilinx, USA
Eduardo de la Torre, Technical University of Madrid, Spain
Suhaib Fahmy, Univeristy of Warwick, UK
Diana Goehringer, Ruhr University Bochum, Germany
Sylvain Guilley, TELECOM-ParisTech, France
Michael Huebner, Ruhr University Bochum, Germany
Herman Lam, University of Florida, USA
Fernanda Lima Kastensmidt, UFRGS, Brazil
Sonia Lopez Alarcon, Rochester Institute of Technology, USA
Martin Margala, University of Massachusetts Lowell, USA
Nele Mentens, KU Leuven, Belgium
Andrew Schmidt, ISI/USC, USA
Dirk Stroobandt, Ghent University, Belgium
Juergen Teich, University of Erlangen-Nuremberg, Germany