3D-Test 2010 - 2010 First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test)

The new 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.

Topic Areas - You are invited to participate and submit your contributions to the 3D-TEST Workshop. The workshop's areas of interest include (but are not limited to) the following topics:

Defects due to Wafer Thinning
Defects in Intra-Stack Interconnects
DfT Architectures for 3D-SICs
EDA Design-to-Test Flow for 3D-SICs
Failure Analysis for 3D-SICs
Known-Good Die / Stack Testing
Pre-Bond and Post-Bond Testing
Reliability of 3D-SICs
Standardization for 3D Testing
System/Board Test Issues for 3D-SICs
Test Cost Modeling for 3D-SICs
Test Flow Optimization for 3D-SICs
Tester Architecture incl. ATE and BIST
Thermal/Mechanical Stress in 3D-SICs
TSV Test, Redundancy, and Repair
Wafer Probing and Probe Damage of 3D-SICs
Submission Instructions - Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found here. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop.

Publications - The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc. A selected subset of papers will be invited to submit an extended journal version of their manuscript for inclusion in a Special Issue of Springer's 'Journal of Electronic Testing - Theory and Applications' (JETTA), being planned for 2011.

Key Dates

Submission deadline : August 23, 2010
Notification of acceptance : October 1, 2010
Camera-ready material : October 22, 2010

Further Information

Yervant Zorian - General Chair
Virage Logic
47100 Bayside Parkway
Fremont, CA 94538, USA
Tel.: +1 (510) 360-8035
Fax: +1 (510) 360-8078
E-mail: yervant.zorian-AT-viragelogic.com

Erik Jan Marinissen - Program Chair
IMEC vzw
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +32 (0)16 28-8755
Fax: +32 (0)16 28-1515
E-mail: erik.jan.marinissen-AT-imec.be