HEART 2016 - 2016 International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

The scope of the meeting includes, but is not limited to:
Architectures and systems:
Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more
Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices
Software and applications:
Novel applications of high-performance computing and Big-data processing with efficientacceleration and custom computing
System software, compilers and programming languages for efficient accelerationsystems / platforms, including many-core processors, GPUs, FPGAs and otherreconfigurable /custom processors
Run-time techniques for acceleration, including Just-in-Time compilation and dynamicpartial-reconfiguration
Performance evaluation and analysis for efficient acceleration
High-level synthesis and design methodologies for heterogeneous, reconfigurable and/orcustom processors/systems