MaRS 2016 - 2016 Workshop on Multicore and Rack-scale Systems (MaRS'16)

Present and future multi-core architectures pose a variety of challenges for system developers: non-cache-coherent memory, heterogeneous processing cores and the exploitation of novel architectural features, such as systems-on-chip (SoCs), distributed switching fabrics, silicon photonics, and programmable hardware. In the near future, we expect to see "rack-scale computers" with 1,000s of cores and terabytes of memory, connected with bandwidth and latency comparable to today's smaller-scale NUMA servers.
MaRS ’16 is a forum for researchers in the hardware, networking, storage, operating systems, language runtime and virtual machine communities to present their experiences with and discuss innovative designs and implementations for these new architectures.