DRSN 2016 - International Workshop on High Performance Dynamic Reconfigurable Systems and Networks (DRSN 2016)

High performance Reconfigurable Systems and Networks on Chips (NoC) have been proposed for SoC applications design to achieve better performance and lower energy consumption when compared to conventional on-chip bus architectures. Recently, there has been a great deal of interest in the development of run-time approaches for reconfigurable systems and networks. These approaches provide techniques that allow RS to autonomously adapt its structure and its behavior to system changes.
Emerging Systems-on-Chip (SoCs), such as those for mobile systems, are typically battery-powered systems and have to support a wide range of streaming applications such as video and audio. Networks-on-chip have been proposed for SoCs applications design to achieve better performance and lower energy consumption when compared to conventional on-chip bus architectures.
Several approaches have been proposed to deal with RS and NoCs and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored to an application domain or a specific application by providing an application-specific RS or NoC. All parameters, such as the on-chip interconnect architecture (i.e., topology), routing, and switching schemes, are defined at design time. However, these should be scalable and adaptive to support various applications by selecting the most suitable parameters based on the requirements of the current application and system conditions.
Recently, there has been a great deal of interest in the development of run-time approaches for reconfigurable systems and NoCs. These approaches provide techniques that allow them to autonomously adapt their structure and their behavior during the course of their operation (i.e., in runtime). For example, the number of VCs (virtual channels) and the buffer size per VC can be dynamically adjusted based on the traffic load and network status.
DRSN 2016 workshop is intended to serve as a forum and bring together the researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of dynamic reconfigurable systems and NoCs. It will cover current and new approaches and relevant activities in the design, analysis, and evaluation of techniques for dynamic reconfigurable systems and NoCs as well as emerging developments.
The DRNS Workshop topics of interest include (but are not limited to) the following:
Reconfigurable computing architectures, models, and tools
Reconfigurable computing design, platforms and development
Reconfigurable computing simulation, synthesis, debugging, verification and testing
Field programmable gate arrays (FPGAs) and other reconfigurable technologies
Dynamic reconfiguration
Reconfigurable computing applications
Topologies reconfiguration for NoCs
Three-Dimensional NoC Design
Reliability, scalability, availability, and fault tolerance
Routing algorithms, switching techniques, and flow control schemes
Reconfigurable Computing for Security and Cryptography
Mapping and scheduling of tasks into NoCs
Self-reconfiguration and self-optimization
Bio-inspired techniques for reconfigurable systems and networks
Analytical evaluation methods for designing reconfigurable NoCs
Area, energy, and performance evaluation
Tools for design space exploration of reconfigurable systems and NoCs
Cases studies and FPGA-based implementation of reconfigurable systems and NoCs
Reconfigurable computing education