VLSI 2016 - Call for Chapters: Design and Modeling of Low Power VLSI Systems

Introduction
Design and Modeling of Low Power VLSI Systems will bring together different advancements reported in hardware design and related technologies. This publication will be useful for academics, researchers, and practitioners seeking the latest practices and knowledge in this field. The proposed book aims for collating the different low power techniques for IC design and classifying them as traditional and modern techniques. It further aims to collate the limiting factors associated with the traditional low power techniques which led to the evolution of new non-traditional methodologies for optimizing power equations.
Objective
Through the book Design and Modeling of Low Power VLSI Systems readers would be able to appreciate the technicalities involved in low power VLSI hardware development process cycle. They would be able to understand the advances in these technologies and their application boundaries limitations. With advances in new capabilities in related domains, new design mechanism have been evolved for ASIC, Semicustom, Custom and other classified design flows along with associated verification process targeting optimized solution on power, performance and area parameters. Readers would be able to appreciate the advancement of related CAD tools associated leading to much needed optimized products. They would be able to understand the basic limiting principles which are proving to be hindrances for further optimizing processes leading to evolvement of an era where new fusion of principles and concepts from different sciences are made and applied to optimize power parameters in VLSI hardware development, design, implementation and verification steps. New trends in power and speed optimization would be illustrated enabling the readers to take advances from these researches and innovative solution approaches. Hence readers would be benefited through the book, covering the development and generation of low power and high performance VLSI hardware modeling and verification techniques.
Target Audience
The target audiences will include graduate students, PhD scholars, faculty members, scientists, and EDA Designers seeking to carry out research / develop an IC design and software application, development for IC design domain covering all steps involved. This book will be useful for perspective users of VLSI low-power circuit developer software applications, including those in involved in developing, testing, and verifying for low power.
Recommended Topics
? Low Power Circuit design methodologies
? Power Aware Design Paradigm
? Conventional Low Power Techniques
? Contemporary Low Power Design Approaches
? Challenge and limitations of low power techniques
? Power modeling techniques
? Advancements of Low Power Modeling
? Tool capabilities for Power Aware Designs
? Power Optimization
? Low power strategies for Beyond Moore’s law era
? Effect and relation of low power techniques wrt speed and area and design parameters
? Application specific low power techniques and their classification for best results
? Thumb rules for high speed/high performance low power design
? System level, architecture level, block level, etc.. low power approaches
? Low power aware logic partitioning,
? Power aware placement and routing strategies
? Utilizing time varying voltage for power aware applications
? Different low power techniques and their boundaries
? Testing Methodologies for Low power IC design and their Advances
? Open Source Tools Assisting Low Power Design
? Low Power bench marking
? Case studies
? Related aspects like power aware hardware-software co-design, focusing on power and its modeling aspects
Submission Procedure
Researchers and practitioners are invited to submit on or before June 30, 2015, a chapter proposal of 1,000 to 2,000 words clearly explaining the mission and concerns of his or her proposed chapter, using instructions on http://www.igi-global.com/publish/call-for-papers/... or directly provide your submission on http://www.igi-global.com/submission/submit-chapte....
Authors will be notified by July 15, 2015 about the status of their proposals and sent chapter guidelines. Full chapters are expected to be submitted by July 30, 2015, and all interested authors must consult the IGI guidelines for manuscript submissions at www.igi-global.com/publish/contributor-resources prior to submission. All submitted chapters will be reviewed on a double-blind peer review basis.
Note: There are no submission or acceptance fees for manuscripts submitted to this book publication, Design and Modeling of Low Power VLSI Systems. All manuscripts are accepted based on a double-blind peer review editorial process.
All proposals should be submitted through the E-Editorial DiscoveryTM online submission manager ( links provided above).
Publisher
This book is scheduled to be published by IGI Global (formerly Idea Group Inc.), an international academic publisher of the “Information Science Reference” (formerly Idea Group Reference), “Medical Information Science Reference,” “Business Science Reference,” and “Engineering Science Reference” imprints. IGI Global specializes in publishing reference books, scholarly journals, and electronic databases featuring academic research on a variety of innovative topic areas including, but not limited to, education, social science, medicine and healthcare, business and management, information science and technology, engineering, public administration, library and information science, media and communication studies, and environmental science. For additional information regarding the publisher, please visit www.igi-global.com. This publication is anticipated to be released in 2016.
Inquiries
Mr. Manoj Sharma
Ex-Com member IEEE India SSCS/CASS
BVCOE, affiliated to GGSIP University, Delhi, India
Email:manojsharma-AT-ieee.org
Ms. Ruchi Gautam
MyResearch Labs, Gr. Noida, INDIA
Email: ruchi-AT-vlsiengineers.in
Dr. Mohammad Ayoub Khan
Computer Science and Engineering, Yanbu Branch
Taibah University, Al Madinah Al Monawarah, KSA & Sharda University, Gr. Noida, INDIA
Email:ayoub-AT-ieee.org