ResearchBib Share Your Research, Maximize Your Social Impacts
Sign for Notice Everyday Sign up >> Login

Co-HPC 2015 - Second International Workshop on Hardware-Software Co-Design for High Performance Computing (Co-HPC 2015)

Date2015-11-16

Deadline2015-08-15

VenueAustin, Texas, USA - United States USA - United States

Keywords

Websitehttps://codaash.org/co-hpc

Topics/Call fo Papers

Hardware-software co-design involves the concurrent design of hardware and software components of complex computer systems, whereby application requirements influence architecture design and hardware constraints influence design of algorithms and software. High Performance Computing (HPC) is facing a daunting challenges as we move towards the exascale era, with the necessity of designing systems that run large-scale simulations with high performance while meeting cost and energy consumption constraints. The purpose of this workshop is to bring together researchers who are investigating the interrelationships between algorithms/applications, systems software, and hardware, and who are developing methodologies and tools for hardware-software co-design for HPC. We seek submissions that address various aspects of hardware-software co-design and that demonstrate collaboration between domain scientists, applied mathematicians, computer scientists, and hardware architects. Last year’s workshop was one of the best attended at SC’14, averaging over 80 attendees throughout the day, with attendees including academic, research lab, and industry researchers and government program managers in the hardware-software co-design area. This year’s workshop focuses especially on hardware-software co-design for advanced architectures, including systems with new low-power processor designs and new memory technologies.
Topics of interest to the workshop include, but are not limited, to the following:
Use of simulation and emulation techniques for co-design
Modeling and prediction of performance and energy consumption
Co-optimization for multiple objectives (such as performance, power, resilience)
Evaluation of new processor and memory technologies for scientific applications
Mapping of algorithms and applications to heterogeneous systems

Last modified: 2015-06-13 14:49:58