MOMAC 2015 - International Workshop on Multi-Objective Many-Core Design (MOMAC)
Topics/Call fo Papers
Semiconductor industry is hitting the utilization wall, resulting in parallel and heterogeneous many-core architectures. Applications have to exploit the available parallelism and heterogeneity to meet their functional and non-functional requirements and to gain performance improvements.
A main challenge originates from many-cores promoting highly dynamic usage scenarios as already observable in today's "smart devices", where multiple and varying numbers of applications are running at different points in time. As a consequence, providing mapping of applications to processor cores which is optimal and predictable with respect to performance, timing, energy consumption, safety, security, etc. may not be guaranteed by static design-time optimization alone. At the same time, pure run-time optimization may result in unpredictable and non-optimal system states. This workshop investigates this field of tension of run-time, design-time, and hybrid design methodologies for the mapping of applications on many-core systems, particularly addressing the aspect of multiple conflicting objectives that drive the design.
This field of research includes numerous intermeshed aspects:
Languages, Models, and Compilers: How to specify, analyze, parallelize, and compile programs which support dynamic usage scenarios in many-cores?
Formal methods, Test, and Verification: How to analyze and verify predictable execution of applications despite unforeseeable run-time events?
Optimization Techniques: Which design-time and run-time techniques as well as combinations of them provide optimized and predictable application mapping for many-cores?
Architecture: Which architectural concepts are required to support predictability, run-time management and (self-)optimization?
A main challenge originates from many-cores promoting highly dynamic usage scenarios as already observable in today's "smart devices", where multiple and varying numbers of applications are running at different points in time. As a consequence, providing mapping of applications to processor cores which is optimal and predictable with respect to performance, timing, energy consumption, safety, security, etc. may not be guaranteed by static design-time optimization alone. At the same time, pure run-time optimization may result in unpredictable and non-optimal system states. This workshop investigates this field of tension of run-time, design-time, and hybrid design methodologies for the mapping of applications on many-core systems, particularly addressing the aspect of multiple conflicting objectives that drive the design.
This field of research includes numerous intermeshed aspects:
Languages, Models, and Compilers: How to specify, analyze, parallelize, and compile programs which support dynamic usage scenarios in many-cores?
Formal methods, Test, and Verification: How to analyze and verify predictable execution of applications despite unforeseeable run-time events?
Optimization Techniques: Which design-time and run-time techniques as well as combinations of them provide optimized and predictable application mapping for many-cores?
Architecture: Which architectural concepts are required to support predictability, run-time management and (self-)optimization?
Other CFPs
- 1th Workshop on Complex Problems over High Performance Computing Architectures
- IIER-The International Conference on Technology, Science, Social Sciences and Humanities
- IIER-International Conference on Civil, Environmental and Medical Engineering
- IIER-International Conference on Science, Technology, Engineering and Management
- IIER-International Conference on Mechanical, Aeronautics and Production Engineering
Last modified: 2014-10-29 22:27:04