INA-OCMC 2015 - 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip
Topics/Call fo Papers
INA-OCMC is a network oriented workshop presenting original work in the field of on-chip, multi-chip interconnection network architecture. The workshop aims at bringing together researchers and engineers from industry and academia to share ideas and thoughts about networking of devices in both the off-chip and the on-chip environment, each with its own design constraints. This is the ninth edition of the workshop. In the previous editions the workshop exhibited a competent audience and interesting discussions arose from the different presentations of authors and from the keynote, thus promoting joint research initiatives.
Call for Papers
Technical Scope
Scalable interconnect architectures form the fabric that unifies future complex computing platforms. The interconnect architecture should be as high performance as the compute nodes, thus enabling the expected exponential growth in system concurrency. The number of nodes either on-chip or off-chip that need to communicate in modern embedded and HPC systems is constantly increasing. This trend poses significant challenges to the interconnection network designers that tackle a multidimensional problem involving hardware and software components such as network interfaces, switches, and communication library APIs. The INA-OCMC workshop focuses on the presentation of novel interconnect architectures, optical and electrical, for embedded MPSoCs/CMPs, Cloud/Datacenter, microservers and HPC systems.
To emphasize both the fundamental impact of silicon photonic technologies on future system and interconnection network architectures and, conversely, the driving forces of practical and economically viable system-level design, requirements and constraints on the underlying technologies, this year the INA-OCMC and SiPhotonics Workshop will be held in a federated fashion. We plan to organize joint keynote presentations and a panel discussion with experts from both fields on topics of interest to both communities. This way, we intend to foster the exchange of ideas and increase collaboration between these highly complementary workshops. The paper submission and review processes will, however, still be run independently by each workshop.
We invite contributions of previously unpublished results on all aspects of emerging interconnect architectures, including but notlimited to:
Networks-on-Chip (NoC)
Multi-Chip Interconnection Networks, including Cluster Interconnects
Communication architectures for 2,5 D and 3D stacked systems
Asynchronous interconnect designs
Switching, buffering, and routing architectures
Interaction with memory hierarchy
Architectures for QoS support
Flow control and congestion management in switching fabrics
Virtualization, SDN, OpenFlow, NFV
Topology exploration
Impact of the interconnect on application performance
Reliability, availability, fault tolerance
Reconfigurable/Programmable interconnect components
Programming models for communication-centric systems
Call for Papers
Technical Scope
Scalable interconnect architectures form the fabric that unifies future complex computing platforms. The interconnect architecture should be as high performance as the compute nodes, thus enabling the expected exponential growth in system concurrency. The number of nodes either on-chip or off-chip that need to communicate in modern embedded and HPC systems is constantly increasing. This trend poses significant challenges to the interconnection network designers that tackle a multidimensional problem involving hardware and software components such as network interfaces, switches, and communication library APIs. The INA-OCMC workshop focuses on the presentation of novel interconnect architectures, optical and electrical, for embedded MPSoCs/CMPs, Cloud/Datacenter, microservers and HPC systems.
To emphasize both the fundamental impact of silicon photonic technologies on future system and interconnection network architectures and, conversely, the driving forces of practical and economically viable system-level design, requirements and constraints on the underlying technologies, this year the INA-OCMC and SiPhotonics Workshop will be held in a federated fashion. We plan to organize joint keynote presentations and a panel discussion with experts from both fields on topics of interest to both communities. This way, we intend to foster the exchange of ideas and increase collaboration between these highly complementary workshops. The paper submission and review processes will, however, still be run independently by each workshop.
We invite contributions of previously unpublished results on all aspects of emerging interconnect architectures, including but notlimited to:
Networks-on-Chip (NoC)
Multi-Chip Interconnection Networks, including Cluster Interconnects
Communication architectures for 2,5 D and 3D stacked systems
Asynchronous interconnect designs
Switching, buffering, and routing architectures
Interaction with memory hierarchy
Architectures for QoS support
Flow control and congestion management in switching fabrics
Virtualization, SDN, OpenFlow, NFV
Topology exploration
Impact of the interconnect on application performance
Reliability, availability, fault tolerance
Reconfigurable/Programmable interconnect components
Programming models for communication-centric systems
Other CFPs
- Instrumentation and Signal Processing Winter School 2015 (ISP WS 2015)
- Eleventh International Conference on Natural Language Processing (ICON-2014)
- FIRST WORKSHOP ON LANGUAGE TECHNOLOGIES FOR INDIAN SOCIAL MEDIA
- 12th International Conference on Mathematics of Program Construction
- 2015 International Conference on Simulation Tools and Techniques
Last modified: 2014-10-12 16:49:43