FSP 2014 - First International Workshop on FPGAs for Software Programmers

The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken. However, to make this happen, there are still important issues to be solved that are in the focus of this workshop.
The FSP Workshop aims at bringing researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends. This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardized target platforms. This will in particular put focus on the requirements of software developers and application engineers. In addition, a distinctive feature of the workshop will be its cross section through all design levels, ranging from programming down to custom hardware. Thus, the workshop is targeting all those who are interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development. In addition, the FSP Workshop shall facilitate collaboration of the different domains.
Topics of the FSP Workshop include, but are not limited to:
High-level synthesis and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
Mapping approaches and tools for heterogeneous FPGAs
Support of hard IP blocks such as embedded processors and memory interfaces
Development environments for software engineers (automated tool flows, design frameworks and tools, tool interaction)
FPGA virtualization (design for portability, resource sharing, hardware abstraction)
Design automation technologies for multi-FPGA and heterogeneous systems
Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility, reliability, or programmability
Operating system services for FPGA resource management, reliability, security
Target hardware design platforms (infrastructure, drivers, portable systems)
Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
Applications (embedded computing, signal processing, big data, bio informatics, database acceleration)
Directions for collaborations (research proposals, networking, Horizon 2020)
Paper submission
Perspective authors are invited to submit original contributions (up to six pages) or extended abstracts describing work-in-progress or position papers (extended abstracts should not exceed two pages). All papers should be submitted in PDF file format following the standard IEEE conference template (http://www.ieee.org/conferences_events/conferences...). Papers may or may not hide author names and affiliation for optional blind reviewing.
All submissions have to be sent via the conference management system EasyChair. Please set up your own personal account if you do not already own an EasyChair account.
Publications
Accepted papers will be included in an ePrint proceedings volume with Open Access. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is due. In addition, selected authors will be invited to contribute a chapter for a book project.
Presentation formats
We are seeking contributions for presentation as oral papers (talk) and posters. Note that the presentation format is independent of the paper length (i.e., regular or short paper). While you will be asked to indicate your preferred presentation format when submitting a paper, the program committee may request an alternative format be considered. The program committee will allocate the format of presentations, taking into account the preference of authors and the balance of the program.
Important dates
Submission deadline:June 30, 2014
Notification of acceptance: July 31, 2014
Camera-ready final version: August 15, 2014
Organization
General Co-Chairs
Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Dirk Koch, University of Manchester, UK
Daniel Ziener, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Program Committee
Hideharu Amano, Keio University, Japan
Jason H. Anderson, University of Toronto, Canada
Gordon Brebner, Xilinx Labs, UK
João M. P. Cardoso, University of Porto, Portugal
Jason Cong, University of California, Los Angeles, USA
Andreas Koch, Technical University of Darmstadt, Germany
Miriam Leeser, Northeastern University, USA
Christian Plessl, University of Paderborn, Germany
Dan Poznanovic, Cray Inc., USA
Rodric Rabbah, IBM Research, USA
Deshanand Singh, Altera, Canada
Satnam Singh, Google, USA
Dirk Stroobandt, Ghent University, Belgium
Markus Weinhardt, Osnabrück University of Applied Sciences, Germany