Racing 2014 - Workshop on Resource-Awareness and Adaptivity in Multi-Core Computing

The steady advances in semiconductor technology allow for increasingly complex SoCs, including multiple (heterogeneous) micro processors, dedicated accelerators, large on-chip memories, sophisticated interconnection networks, and peripherals. However, design, verification, and test as well as parallel programming of such complex multi-core architectures are very challenging since they may have to deal with highly dynamic workloads in different application scenarios and environments. In addition, the architecture might alter itself, either intentionally (e.g., dynamic voltage/frequency scaling, power management) or unintentionally (e.g., failures, aging).
As a remedy, one recent research trend in multi-core computing is to design control loops across all platform layers, from application and run-time software down to the status of the underlying hardware. Concepts such as resource-aware programming and adaptive computing are promising candidates for optimizing multi-core systems at run-time with respect to several objectives (utilization, performance, temperature, energy, reliability, dependability, etc.). On the other hand, the enhanced flexibility and adaptivity of such systems raises questions on the predictability of program execution.
The Racing Workshop aims at bringing together researchers and experts from both academia and industry to discuss and exchange research advances from different disciplines in design and test of multi-core architectures as well as programming and run-time management. A distinctive feature of the workshop is its cross section through the entire software/hardware stack, ranging from programming down to multi-core hardware. Thus, Racing is targeted for all of those who are interested in understanding the big picture and the potential of resource-aware and adaptive multi-core computing, its challenges, available solutions, and enables for collaboration of the different domains.
Topics of the Racing Workshop include, but are not limited to:
Resource-aware programming, adaptive computing, and self-x properties
Resource management, online learning and tuning
Fault tolerance in multi-core systems at hardware and software level
Testability, prototyping, and debugging of multi-core architectures
Multi-core {timing, power, fault, reliability} predictability, security, safety, and performance modeling
Verification and validation of multi-core architectures
Paper submission
Perspective authors are invited to submit an extended abstract (max. 6 pages) or work in progress (2 pages). All papers should be formatted as follows: A4 or letter pages, double column, single spaced, Times or equivalent font of minimum 10pt. All submissions have to be sent via the conference management system EasyChair. Please set up your own personal account if you do not already own an EasyChair account.
Publications
Accepted papers will be published on the workshop’s web page. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is submitted. In addition, authors will be invited to submit an extended version of their papers for publication in a journal's special issue, which will be announced at a later point in time.
Important dates
Submission deadline:March 15, 2014
Notification of acceptance: April 15, 2014
Camera-ready final version: April 30, 2014
Organization
General Chair
Jürgen Teich, University of Erlangen-Nuremberg, Germany
Program Chair
Frank Hannig, University of Erlangen-Nuremberg, Germany
Program Committee
Iuliana Bacivarov, ETH Zürich, Switzerland
Andreas Herkersdorf, TU München, Germany
Christoph Kessler, Linköping University, Sweden
Sébastien Pillement, University of Nantes, France
Andy D. Pimentel, University of Amsterdam, Netherlands
Thomas Schweizer, University of Tübingen, Germany