AASC 2014 - International Workshop on Architecture-aware Simulation and Computing (AASC 2014)

With multi- and many-core based systems, performance increase on the microprocessor side will continue according to Moore's Law, at least in the near future. However, the already existing performance limitations due to slow memory access are expected to get worse with multiple cores on a chip, and complex hierarchies of cache memory will make it hard for users to fully exploit the theoretically available performance. In addition, the increasingly hybrid and hierarchical design of compute clusters and high-end supercomputers, as well as the use of accelerator components (Cell BE or GPGPUs, e.g.) add further challenges to efficient programming in HPC applications.
Therefore, compute and data intensive tasks can only benefit from the hardware’s full potential, if both processor and architecture features are taken into account at all stages ? from the early algorithmic design to the final implementation.
The AASC workshop strives to address all aspects related to these issues, including, but not limited to:
Hardware-aware, compute- and memory-intensive simulations of real-world problems in computational science and engineering (for example, from applications in electrical, mechanical, civil, or medical engineering).
Architecture-aware approaches for large-scale parallel simulations in both implementation and algorithm design, including scalability studies.
Architecture-aware parallelisation on HPC platforms; esp. platforms with hierarchical communication layout, multi-/many-core platforms, NUMA architectures, or accelerator components (Cell BE, GPU, FPGA).
Parallelisation with appropriate programming models and tool support for multi-core and hybrid platforms.
Software engineering, code optimisation, and code generation strategies for parallel systems with multi-core processors.
Tools for performance and cache behavior analysis (including cache simulation) for parallel systems with multi-core processors.
INSTRUCTIONS FOR PAPER SUBMISSIONS:
You are invited to submit original and unpublished research works on above and other topics related to Architecture-aware Simulation and Computing. Submitted papers must not have been published or simultaneously submitted elsewhere. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and email addresses. Please, indicate clearly the corresponding author and include up to 6 keywords from the above list of topics and an abstract of no more than 400 words. The full manuscript should be at most 8 pages using the two-column IEEE format. Additional pages will be charged additional fee. Short papers (up to 4 pages), poster papers and posters (please refer to http://hpcs2014.cisedu.info/home/posters for the posters submission details) will also be accepted for submission. In case of multiple authors, an indication of which author(s) is responsible for correspondence must be indicated. Please include page numbers on all submissions to make it easier for reviewers to provide helpful comments.
Submit a PDF copy of your full manuscript to the Workshop submission site at XXX . Acknowledgement will be sent within 48 hours of submission.
Only PDF files will be accepted. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, contributions, technical clarity and presentation. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. Authors of accepted papers must guarantee that their papers will be registered and presented at the workshop.
PROCEEDINGS
Accepted papers will be published in the conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2014 web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is to be published as ISBN proceedings by the IEEE and will be available online through IEEE Digital Library and indexed by major indexing services accordingly (e.g., EI indexing).
If you have any questions about paper submission or the workshop, please contact the workshop organizers.