DMCC 2014 - 6th Workshop on Dependable Many-Core Computing (DMCC 2014)

Today, the integration of many cores is quite common - and the end of the road is not in sight. These many-core architectures bring up unprecedented capabilities, opportunities, as well as challenges. The more transistors are integrated on a chip and the more cores are introduced, the more faults can be asserted. These faults arise either during fabrication or operation. As the fabrication costs are continuously rising, it is most important to increase the output of a fab by software, architectural, or physical means. This workshop addresses issues and solutions through dependable software and/or hardware design of many-core systems.
The DMCC Workshop topics of interest include (but are not limited to) the following:
Dependable Many-Core Architectures
Power-Aware Many-Core Design
Dependable & Secure Many-Core Designs
Many-Core Development and Design Tools
Simulation Techniques
System-Level Many-Core Implementation
Many-Core Interconnect Technology
Many-Core System-On-Chip Development
Reconfigurable Computing and FPGAs
Design for Testing
Hardware and Software Debug Facilitie
Many-Core Programming and Optimization
Application Partitioning and Load Balancing
Hypervisors and Virtual Machine Technology
Trusted and Untrusted Environments
Virtualization for Dependability
Dependability through Multi-Threading
Fault Detection on the Physical Layer
Fault-Tolerant Software Design
Fault-Tolerant Hardware Design
Fault-Tolerant HW/SW Co-Design