SLIP 2014 - SLIP '14 System Level Interconnect Prediction Workshop
Date2014-06-01 - 2014-06-02
Deadline2014-03-01
VenueSan Francisco, USA - United States
Keywords
Websitehttps://sliponline.org
Topics/Call fo Papers
SLIP '14 System Level Interconnect Prediction Workshop
June 01 - 02, 2014
San Francisco, CA, USA
Authors of accepted papers must sign an ACM copyright release form for their papers.
Representative technical topics include, but are not limited to:
1. Interconnect prediction and optimization at various IC design stages
2. Interconnect design challenges and system-level NoC design
3. Design and analysis of power and clock networks
4. Interconnect architecture of structural designs and FPGAs
5. Interconnect fabrics of many-core architectures
6. Design-for-manufacturing (DFM) techniques for interconnects
7. High speed chip-to-chip interconnect design
8. Design and analysis of chip-package interfaces
9. Interconnect topologies of multiprocessor systems
10. 3D interconnect design and prediction, including TSV architecture and monolithic 3D stacking
11. Emerging interconnect technologies, e.g., RF interconnects, photonic networks, carbon-based interconnects, etc.
12. Synergies between chip communication networks and networks arising in other contexts such as social networks, system biology, etc
General Chair
Mustafa Ozdal
Intel, USA
Technical Program Chair
Rasit O. Topaloglu
IBM, USA
Finance Chair
Sung Kyu Lim
Georgia Institute of Technology, USA
Panel Chair
Baris Taskin
Drexel University, USA
Publication Chair
Tsung-Yi Ho
National Cheng Kung University, Taiwan
Publicity Chair
Zhuo Li
IBM Austin Research Lab, USA
Steering Committee Members
Chuck Alpert
IBM, USA
Chung-Kuan Cheng
University of California, San Diego, USA
Giovanni De Michelli
Ecole Polytechnique Federale de Lausanne, Switzerland
Andrew B. Kahng
University of California, San Diego, USA
Michael Kishinevsky
Intel, USA
Sherief Reda
Brown University, USA
Program Committee Members
Chris Chu
Iowa State University, USA
Tsung-Yi Ho
National Cheng Kung University, Taiwan
Hui-Ru Jiang
National Chiao Tung University, Taiwan
Andrew B. Kahng
University of California at San Diego, USA
Youngmin Kim
UNIST, Korea
Bin Li
Intel, USA
Zhuo Li
IBM, USA
Jens Lienig
Dresden University of Technology, Germany
Sung Kyu Lim
Georgia Institute of Technology, USA
Mustafa Ozdal
Intel, USA
Sherief Reda
Brown University, USA
Baris Taskin
Drexel University, USA
Rasit O. Topaloglu
IBM, USA
Natarajan Viswanathan
IBM, USA
Gustavo Wilke
Intel, USA
June 01 - 02, 2014
San Francisco, CA, USA
Authors of accepted papers must sign an ACM copyright release form for their papers.
Representative technical topics include, but are not limited to:
1. Interconnect prediction and optimization at various IC design stages
2. Interconnect design challenges and system-level NoC design
3. Design and analysis of power and clock networks
4. Interconnect architecture of structural designs and FPGAs
5. Interconnect fabrics of many-core architectures
6. Design-for-manufacturing (DFM) techniques for interconnects
7. High speed chip-to-chip interconnect design
8. Design and analysis of chip-package interfaces
9. Interconnect topologies of multiprocessor systems
10. 3D interconnect design and prediction, including TSV architecture and monolithic 3D stacking
11. Emerging interconnect technologies, e.g., RF interconnects, photonic networks, carbon-based interconnects, etc.
12. Synergies between chip communication networks and networks arising in other contexts such as social networks, system biology, etc
General Chair
Mustafa Ozdal
Intel, USA
Technical Program Chair
Rasit O. Topaloglu
IBM, USA
Finance Chair
Sung Kyu Lim
Georgia Institute of Technology, USA
Panel Chair
Baris Taskin
Drexel University, USA
Publication Chair
Tsung-Yi Ho
National Cheng Kung University, Taiwan
Publicity Chair
Zhuo Li
IBM Austin Research Lab, USA
Steering Committee Members
Chuck Alpert
IBM, USA
Chung-Kuan Cheng
University of California, San Diego, USA
Giovanni De Michelli
Ecole Polytechnique Federale de Lausanne, Switzerland
Andrew B. Kahng
University of California, San Diego, USA
Michael Kishinevsky
Intel, USA
Sherief Reda
Brown University, USA
Program Committee Members
Chris Chu
Iowa State University, USA
Tsung-Yi Ho
National Cheng Kung University, Taiwan
Hui-Ru Jiang
National Chiao Tung University, Taiwan
Andrew B. Kahng
University of California at San Diego, USA
Youngmin Kim
UNIST, Korea
Bin Li
Intel, USA
Zhuo Li
IBM, USA
Jens Lienig
Dresden University of Technology, Germany
Sung Kyu Lim
Georgia Institute of Technology, USA
Mustafa Ozdal
Intel, USA
Sherief Reda
Brown University, USA
Baris Taskin
Drexel University, USA
Rasit O. Topaloglu
IBM, USA
Natarajan Viswanathan
IBM, USA
Gustavo Wilke
Intel, USA
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Last modified: 2014-01-08 23:56:43