VTS 2014 - The IEEE VLSI Test Symposium

The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, debug and repair of microelectronic circuits and systems.
The VTS Program Committee invites original, unpublished paper submissions for VTS 2014. Paper submissions should be complete manuscripts, up to six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status.
PROGRAM CHAIR
Yiorgos Makris
The University of Texas at Dallas
yiorgos.makris-AT-utdallas.edu
GENERAL CHAIR
Claude Thibeault
École de technologie supérieure
Claude.Thibeault-AT-etsmtl.ca
VTS Topics
Major topics include, but are not limited to:
Analog, Mixed-Signal & RF Test
ATPG & Compression
ATE Architecture & Software
Built-In Self-Test (BIST)
Defect & Current Based Test
Defect/Fault Tolerance
Delay & Performance Test
Design for Testability (DFT)
Design Verification/Validation
Diagnosis & Debug
Embedded System & Board Test
Embedded Test Methods
Emerging Technologies Test
FPGA Test
Fault Modeling & Simulation
Hardware Security
Low-Power IC Test
Microsystems, MEMS & Sensor Test
Memory Test & Repair
On-Line Test & Error Correction
Power & Thermal Issues in Test
System-on-Chip (SOC) Test
Test Standards
Test Economics
Test of Biomedical Devices
Test of High-Speed I/O
Test Quality & Reliability
Test Resource Partitioning
Transients & Soft Errors
2.5D, 3D and SiP Test