WISH 2010 - WISH 2010- Workshop on Infrastructures for Software/Hardware co-design

WISH - Workshop on Infrastructures for Software/Hardware co-design
A major hindrance to the development of co-designed hardware and software systems is the availability of fast, accurate, and reliable infrastructures for performance evaluation and analysis. Simultaneously varying both the software and hardware components of a system introduces complexities which render traditional evaluation methodologies unusable.
Traditional evaluation methodologies assume that either the hardware or the software components of a system are fixed. For example, an accepted methodology for evaluating the effectiveness of a compiler optimization is to compare the execution of two differently compiled binaries on the same hardware. Likewise, an accepted methodology for evaluating microarchitectural hardware changes has been to measure relatively short, but representative, samples of the same program's execution with multiple configurations of a detailed timing simulator.

Nonetheless, the co-design of hardware and software systems is being pursued as part of many industry and academic projects. Researchers have therefore been forced to build their own custom infrastructures and invent methodologies to demonstrate the viability of their ideas. The purpose of this workshop is for experienced practitioners in this area to share their gained expertise and knowledge to a wider audience in the hopes of broadening community understanding. Identifying readily-available building blocks and tools, as well as opportunities for further improvements in this area are the goals of this workshop.

Topics of interest include, but are not limited to:

Trace-based and simulation-based infrastructures
FPGA-based prototyping
Performance analysis tools and profiling techiques
Algorithms and representations for co-design
Design and optimization of novel architectures
System design
Language support for dynamic optimization
Software to hardware mapping
Novel methodologies for evaluating co-designed:
Mobile environments
Virtual execution environments
Dynamic optimization techniques
Static compilation techniques
Graphics systems
Memory systems, including transactional and consistency models
Parallelization detection/exploitation techniques
Important Dates

February 28th 2010 (midnight PST): Extended Abstracts Due
March 21th 2010: Notification of Acceptance
April 11th 2010 (midnight PST): Final version of 20 minute presentation due
April 25th 2010: Workshop date
Submissions guidelines

Authors should submit a 3 page double spaced extended abstract by February 28th, 2010 to anne-AT-vmware.com. Final submission is a slide set for a 20 minute presentation.

To allow authors to use the workshop to solicit feedback on work to be submitted for future publication, please note that submissions will not be published in the CGO 2010 proceedings.
General Chair

Anne Holler, VMware
Program Co-Chairs

Edson Borin, Intel
Uma Srinivasan, Intel

Program Committee

Anne Holler, VMware
Jim Callister, Intel
Nadya Bliss, MIT Lincoln Laboratory
Naveen Kumar, VMware
Shih-Wei Liao, Google
Yukinori Sato, Japan Advanced Institute of Science and Technology (JAIST)