ResearchBib Share Your Research, Maximize Your Social Impacts
Sign for Notice Everyday Sign up >> Login

HEART 2014 - International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

Date2014-06-09 - 2014-06-11

Deadline2014-02-01

VenueSendai Miyagi, Japan Japan

Keywords

Websitehttps://www.cs.tsukuba.ac.jp/~yoshiki/he...

Topics/Call fo Papers

The HEART symposium is an international forum on state-of-the-art research in high-performance and power-efficient computing using accelerator technologies such as FPGAs, GPGPUs, and/or specialized accelerators. The fifth edition of HEART will take place in Sendai Miyagi, Japan.
Scope
The scope of the meeting includes, but is not limited to:
Architectures and systems:
Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more
Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices
Software and applications:
Novel applications of high-performance computing and Big-data processing with efficientacceleration and custom computing
System software, compilers and programming languages for efficient accelerationsystems / platforms, including many-core processors, GPUs, FPGAs and otherreconfigurable /custom processors
Run-time techniques for acceleration, including Just-in-Time compilation and dynamicpartial-reconfiguration
Performance evaluation and analysis for efficient acceleration
High-level synthesis and design methodologies for heterogeneous, reconfigurable and/orcustom processors/systems
FPGA Design Contest 2014 (Blocus Duo Revenge)
The details will be announced at this webpage at the end of December.
Important dates (UTC+0):
Paper submission: February 1, 2014 (tentative)
Author notification: March 1, 2014
Camera-ready due: April 1, 2014
Workshop Dates: June 9-11, 2014

Last modified: 2013-08-09 20:52:07