MULTIPROG 2014 - Seventh Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2014)

Computer manufacturers have already embarked on the multi-core roadmap, promising to add more and more cores/hardware threads on a chip: many-cores are on the horizon. This shift to an increasing number of cores and heterogeneous architectures has placed new burdens on the programming community. Until now, software has been developed with a single processor in mind and it needs to be parallelized and optimized for accelerators such as GPUs to take advantage of the new breed of multi-/many-core computers. As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand.
The seventh edition of the MULTIPROG workshop aims to bring together, and cause fruitful interaction between, researchers interested in programming models and their implementation and in computer architecture, with special emphasis on heterogeneous architectures. A wide spectrum of issues are central themes for this workshop such as what the future programming models should look like to accelerate software productivity, how compilers, run-times and architectures should support these new programming models, innovative algorithms and data structure development, and heterogeneous embedded, accelerated systems.
MULTIPROG is intended for quick publication of early results, work-in-progress, etc, and is not intended to prevent later publication of extended papers. Informal proceedings with accepted papers will be made available at the workshop.
Topics of interest
Papers are sought on topics including, but not limited to:
Multi-core architectures
Architectural support for compilers/programming models
Processor (core) architecture and accelerators, in particular GPUs
Memory system architecture
Performance, power, temperature, and reliability issues
Heterogeneous computing
Algorithms and data structures for heterogeneous systems
Applications for heterogeneous computing and real-time graphics
Programming models for multi-core architectures
Language extensions
Run-time systems
Compiler optimizations and techniques
Benchmarking of multi-/many-core architectures
Tools for discovering and understanding parallelism
Tools for understanding performance and debugging
Case studies and performance evaluation
Important dates
Abstract Submission: October 4, 2013
Final Submission: October 11, 2013
Author Notification: November 26, 2013
Paper Submission
Submitted papers should use the LNCS format and should be 12 pages maximum. Manuscript preparation guidelines can be found at the LNCS web site. Please check that (i) pages are numbered, and (ii) graphs etc. remain legible when printed in black and white.
Organizers
Eduard Ayguade UPC/Barcelona Supercomputing Center Spain eduard-AT-ac.upc.edu
Benedict R. Gaster Qualcomm USA bgaster-AT-qti.qualcomm.com
Lee Howes Advanced Micro Devices USA lee-AT-fidgetfiction.co.uk
Per Stenstrom Chalmers University of Technology Sweden pers-AT-chalmers.se
Osman Unsal BSC-Microsoft Research Centre Spain osman.unsal-AT-bsc.es