RePP 2014 - Workshop on Reconciling Performance with Predictability (RePP)

The RePP workshop is concerned with embedded systems that are characterized by efficiency requirements on the one hand and critical constraints on the other. Such systems occur in many industry-relevant embedded application domains such as avionics, automotive, railway systems, power plants, construction machinery, and robotics.
Offline guarantees for the satisfaction of critical constraints have to be derived by appropriate methods. The difficulty of deriving guarantees strongly depends on the predictability properties of the systems, in particular of the employed processor architecture, the software design discipline, the operating system including the scheduling strategy, the communication mechanism, and the used middleware. However, at the same time, system efficiency is measured by means of average-case behaviour under different criteria such as performance, utilization of resources, and power consumption.
Unfortunately, it can be observed that in computer system design the gap between average-case and worst-case behaviour increases rapidly. The technical reasons for the limited time-predictability are well known, for example the variation and non-determinism of the system environment and the interference caused by the use of shared resources.
The workshop will discuss approaches that atttack the combination of the two goals, the improvements of worst-case predictability and of average-case performance, on all system layers and in the layering principle itself. Predictable architectures, resource-aware compilers, scheduling considering worst-case and average-case performance will be considered. Of particular importance will be the abstraction mechanism used for structuring systems, which has to consider resources as first-class citizens.
Goals:
Capture requirements of relevant application domains.
Clarify the notion of Timing Predictability.
Present existing approaches to reconciling predictability and performance.
Investigate hardware and software design recommendations to allow for predictable multicore processors and timing predictable parallel software.
Participants:
Researchers in safety-critical embedded systems.
Safety-critical industry, e.g. aeronautics, automotive, defence.