WTASSM 2013 - 1st Workshop on Timing Analysis and Synthesis for Synchronous Models

WTASSM 2013 workshop invites submissions from all areas related to the timing properties of both digital and analog electronic systems, including but not limited to:
Transistor level models
Analog circuit modeling
Timing interfaces with mixed signal circuits
Reliability modeling and simulation
Circuit-level simulation of digital circuits
Simulation and characterization of SRAM circuits
Digital cell characterization for many corner/statistical timing
Timing-driven system design, synthesis and physical design
Sensitivity analysis
Full custom design analysis
Integrated functional-temporal analysis
Timing issues in low power design and testing
Power-delay trade-offs
Delay models and metrics
Layout impact on timing
Timing-driven layout optimization
Timing-driven synthesis and re-synthesis
Circuit optimization
Uncertainty-based analysis
Incorporation of manufacture impacts to timing
Reliability impact on performance
Process & environmental variation models
Statistical analysis technique
Clocking, synchronization, and skew
Clock domains, static/dynamic logic
Novel clocking and no-clock (Asynchronous) schemes
Timing implications of emerging technologies