ROME 2013 - Workshop on Runtime and Operating Systems for the Many-core Era

Since the beginning of the multicore era, parallel processing has become prevalent across the board. However, in order to continue a performance increase according to Moore's Law, a next step needs to be taken: away from common multicores towards innovative many-core architectures. Such systems, equipped with a significant higher amount of cores per chip than multicores, pose challenges in both hardware and software design. On the hardware side, complex on-chip networks, scratchpads and memory interfaces as well as cache-hierarchies, cache-coherence strategies and the building of coherency domains have to be taken into account.
However, the ROME workshop focuses on the software side because without complying system software, runtime and operating system support, all these new hardware facilities cannot be exploited. Hence, the new challenges in hardware/software co-design are to step beyond traditional approaches and to wage new programming models and OS designs in order to exploit the theoretically available performance as effectively as possible.
Topics
The focus of this workshop stands in the tradition of a successful series of events hosted by the Many-core Applications Research Community (MARC). Although this workshop is not considered as a self-contained MARC symposium, the organizers and several members of the tentative program committee are part of the MARC community. Authors from all related disciplines are invited to submit unpublished papers regarding software for novel many-core hardware architectures.
Operating system support for novel many-core architectures
Many-core aware runtime support for large-scale applications
Virtualization solutions to deal with hardware limitations
Tools for performance analysis on many-core systems
Dealing with legacy software on novel many-core architectures
New approaches for leveraging on-die messaging facilities
Experiences porting, running, or developing applications
Traditional and new programming models for novel many-core hardware
Bare-metal programming and system software
Power-aware many-core computing