ViPES 2013 - 1st Workshop on Virtual Prototyping of Parallel and Embedded Systems ViPES

The 1st Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES 2013) will be held in Boston, USA in May 2013. ViPES 2013 is associated with the 27th Annual International Parallel & Distributed Processing Symposium (IPDPS 2013) and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing.
Aim
Virtual prototyping stands for the development of hardware/software systems without using a real hardware prototype, i.e. no printed circuit board with electronic devices such as processors, field programmable gate arrays, peripherals and other devices is needed. The advantage is the possibility to exchange parts in the system setup with faster turnaround times in comparison to the traditional development process, where a time consuming redesign of the complete board has to be done. Since some years, the community exploiting these novel methods has grown as time to market plays a major role in industry. Additionally, the increasing complexity of embedded systems, which are more and more realized as parallel and distributed cyber-physical system, forces to perform a time-consuming design space exploration. For academics virtual prototyping is a hot topic and is used to develop future systems and to enable an outlook into the next generation of embedded systems and devices. The wide range of application scenarios for this type of development includes amongst others automotive, avionics, railway and medicine applications. This workshop targets the domain of virtual prototyping focusing the following topics:
- Virtual prototyping development tools
- Methods for virtual prototyping of complex systems
- Application development with virtual platforms
- Methods for Hardware / Software Codesign with virtual platforms
- Design space exploration for parallel and distributed multicore and cyber-physical systems
- Estimation of system characteristics in an early stage of development
- Functional verification at a high level of abstraction
- Methods for modeling of IP cores with SystemC
- Usage of Architecture Description Languages (ADL) for IP core development
Submission guideline
All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript (not to exceed 6 pages of single spaced text, including figures and tables. Submissions should be in PDF-format. Templates for paper preparation can be found at: http://www.ieee.org/web/publications/pubservices/c...
IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press as a CD-ROM disk. Submitted papers should not have appeared in or be under consideration for a different workshop or conference. The 5 best ranked papers (according to the review results) will be invited to submit an extended version to ACM TECS journal.
Important Dates
Submission deadline: December 21st
Decision notification: February 1st
Camera ready paper due: February 28st
Submission interface:
The submission interface via EDAS is available under