MCMC 2013 - Workshop 2013 “Integration of mixed-criticality subsystems on multi-core processors”

Modern embedded applications typically integrate a multitude of functionalities with potentially different criticality levels into a single system. Without appropriate preconditions, the integration of mixed-criticality subsystems can lead to a significant and potentially unacceptable increase of engineering and certification costs. A promising solution is to incorporate mechanisms that establish multiple partitions with strict temporal and spatial separation between the individual partitions. In this approach, subsystems with different levels of criticality can be placed in different partitions and can be verified and validated in isolation. This workshop focuses on solutions for the integration of mixed-criticality subsystems on multi-core processors.
Workshop Scope
In the near future most processors will be based on multi-core technology, which poses fundamentally new challenges on many embedded application domains. In this workshop you will learn how to employ multi-core technology in embedded applications that are safety-critical and have stringent requirements on real-time properties and certification aspects. In particular the following aspects were conveyed:
Multi-Processor Systems-on-a-Chip (MPSoCs) for mixed-criticality applications
Hypervisors and operating systems for MPSoCs
Hard real-time guarantees & certification aspects
Model-driven engineering tools for effort reduction
Application in automotive, avionics, railway, energy and industrial control
Existing projects and future research directions