SELSE 2013 - SELSE 2013 : IEEE Workshop on Silicon Errors in Logic - System Effects

The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). We are soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.
Key areas of interest are (but not limited to):
Technology trends and the impact on error rates
New error mitigation techniques
Characterizing the overhead and design complexity of error mitigation techniques
Case studies describing the engineering tradeoffs necessary to decide what mitigation technique to apply
Experimental data
System-level models: derating factors and validation of error models
Error handling protocols (higher-level protocols for robust system design)
Authors are requested to submit extended abstracts for review before December 14, 2012. Extended abstracts will be considered for both oral and poster presentation. All accepted submissions are included in the workshop proceedings. Authors will be notified of paper outcome by February 2, 2013. Camera-ready papers are due on March 4, 2013.
Additional information and guidelines for submission are available at www.selse.org. Submissions should be PDF or Microsoft Word files in IEEE format that do not exceed four printed pages. Camera-ready papers can be up to six pages in length in IEEE format. Papers are not made available through IEEE and authors retain the copyright of their work. Authors may optionally choose to make their final papers available online through the SELSE webpage.
Important dates:
Extended abstract submission: December 14, 2012
Authors notification: February 2, 2013
Camera-ready submission: March 4, 2013
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The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.
Last Updated on Monday, 10 September 2012 07:44
Thanks to our sponsors
The SELSE workshop committee is very thankful for our sponsors.
SELSE provides a forum for discussing current research and practices in system-level management of transient errors ? both intermittent and soft, due to manufacturing and design failures or high-energy particle bombardments.
Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). The organizing committee of this workshop consists of a group of leading researchers and architects/designers in the areas of devices, products, and systems reliability. We solicit papers that cover system-level effects of errors from a wide variety of perspectives: architectural, logical and circuit-level, and semiconductor processes. Case studies are also solicited.
One of our main goals since the inception of this workshop has been to ensure that graduate students have as much of an opportunity as possible to participate in SELSE. To date, we have used corporate contributions to hold the student registration fee under $75 while allowing them to participate in all events, including the banquet. We greatly appreciate corporate support, and recognize our supporters on the website, in the printed proceedings, and on signage at the workshop.
There are four sponsorship levels: basic for $500, silver for $1000, gold for $1500, and platinum for $2000 or higher with a commensurate level of written and/or verbal acknowledgement in the workshop, proceedings, and website. If you are interested in being a sponsor, contact the TTTC office at:
TTTC Office c/o IEEE Computer Society
Attn: Meredith M. Griffith
1 Marsh Elder Lane
Savannah, GA 31411
If an invoice or W-9 is needed, please send company name, contact name, address, phone, email and sponsorship amount to the above address or to meredith-AT-cemamerica.com. IEEE Federal ID# is 13-1656633.