WRTLT 2012 - 2012 Ieee The 13Th Workshop On Rtl And High Level Testing

The purpose of this workshop is to bring researchers and practitioners of LSI testing from all over the world together to exchange ideas and experiences in register transfer level (RTL) and high level testing. WRTLT'12, the thirtheenth workshop, will be held in conjunction with the 21st Asian Test Symposium (ATS'12) in Niigata, Japan. We hope and expect this workshop provides an ideal forum for frank discussion on this important topic for the future system-on-a-chip(SoC) devices and 3D ICs. Areas of interest include but are not limited to:
- High level Testing : RTL/Behavior level testing, High level approaches for testing, RTL ATPG, RTL DFT, RTL BIST, High level synthesis for testability, Relationship between RTL and gate level testing, Functional fault modeling,
- High level test bench generation
- 3D IC Testing
- SoC/Noc Testing: Test scheduling, Core testing, Interconnect testing
- Reliable SoC : System level reliability, Self repair, Fault tolerant SoC
- Microprocessor Testing
- Design Verification
- Gate Level Test Related Issues : Low power testing, Test compression, ATPG, DFT, BIST
- Secure Testing
- Hardware Trojan Detection
SUBMISSIONS
Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper and should include: title, full name and affiliation of all authors, 50 words abstract, keywords and the name of contact author. All papers should be submitted as PDF files to:
wrtlt12paper-AT-ieee-wrtlt.org