EESC 2012 - First international Workshop on Energy Efficiency in Supercomputing (EESC 2012)
Topics/Call fo Papers
One of the major challenges on the way towards exascale computing is the ever growing demand in electrical power and energy that HPC systems consume. The reasons are the ever growing number of transistors on the processors and the steep increase in the number of processors in order to accelerate the pace of HPC systems. The increased parallelism requires more system infrastructure (e.g., interconnect, memory, I/O nodes, and cooling) in order to harness most of the available compute power. This parallelism in turn leads to higher system power levels and energy consumption, which requires a bigger support infrastructure (e.g., building design, power supply, and cooling) to handle the increased power and cooling requirements.
The challenge that the HPC community faces in the next decade will be to reduce the power requirements on every level of HPC systems while still increasing compute performance. This workshop will provide a forum for researchers to present and to exchange ideas concerning power monitoring, modeling and saving methods for all levels of HPC.
Topics
Power-aware HPC architectures
Models for power and performance aware optimizations (energy-to-solution)
Profiling tools for power and performance
Energy-efficient infrastructure: power, cooling, and energy recycling
Energy-aware analysis techniques
Power-aware networks in HPC
Automatic energy tuning of single applications
Energy saving methods in processors
The workshop is supported by AutoTune, an FP7 project that focuses on automatic performance and energy tuning.
Important Dates:
April 2nd: submission deadline
May 7th: author notification
May 20th: camera ready papers due
June 29th: workshop
All submissions will undergo a review by at least two reviewers. We welcome submissions of full papers not exceeding 10 pages in Springer LNCS format presenting unpublished work which will be published in a workshop proceeding. The authors of the best papers will be invited to submit an extended version for a special issue of the Springer Computing Journal. Please send your submissions via EasyChair.
The challenge that the HPC community faces in the next decade will be to reduce the power requirements on every level of HPC systems while still increasing compute performance. This workshop will provide a forum for researchers to present and to exchange ideas concerning power monitoring, modeling and saving methods for all levels of HPC.
Topics
Power-aware HPC architectures
Models for power and performance aware optimizations (energy-to-solution)
Profiling tools for power and performance
Energy-efficient infrastructure: power, cooling, and energy recycling
Energy-aware analysis techniques
Power-aware networks in HPC
Automatic energy tuning of single applications
Energy saving methods in processors
The workshop is supported by AutoTune, an FP7 project that focuses on automatic performance and energy tuning.
Important Dates:
April 2nd: submission deadline
May 7th: author notification
May 20th: camera ready papers due
June 29th: workshop
All submissions will undergo a review by at least two reviewers. We welcome submissions of full papers not exceeding 10 pages in Springer LNCS format presenting unpublished work which will be published in a workshop proceeding. The authors of the best papers will be invited to submit an extended version for a special issue of the Springer Computing Journal. Please send your submissions via EasyChair.
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Last modified: 2012-03-07 19:51:49