NovelMP 2012 - Workshop on Novel Trends for Multicore Programming, Design and Hardware Architectures NovelMP 2012

For the next decade, Moore’s Law is still going to provide higher transistor densities allowing billions of transistors to be integrated on a single chip. However, it has become obvious that exploiting the transistor budget for instruction-level parallelism, deeper pipelines, and superscalar techniques has come to an end. Especially scaling performance by higher clock frequencies is getting more and more difficult due to heat dissipation problems and energy consumption. The latter is not only a technical problem for mobile systems, but is even going to become a severe problem for computing centers, where energy already is a significant cost factor. Further performance improvements can only be achieved by exploiting parallelism at all system levels.
Multicore architectures offer a better performance/Watt ratio than single core architectures with similar performance. The combination of multicore and coprocessor technology promises a significant increase of computing power for compute-bound applications. FPGA-based accelerators not only offer the opportunity to increase application performance by implementing their compute-intensive kernels in hardware, but also to adapt to the dynamic behavior of an application.
The purpose of this workshop is to evaluate novel paradigms for designing and programming future MPSoC architectures. The main emphasis is on (reconfigurable) architectures, design flow, tool development, as well as applications and system design.

Topics of interest include, but are not limited to:
- Programming models
- Homogeneous / heterogeneous and hybrid multicore architectures
- Design methods (hardware/software codesign, compilation techniques)
- Run-time support (run-time systems, operating systems)
- Reconfiguration techniques (adaptive hardware, FPGA)
- Simulation and prototyping (performance analysis, verification)
- Applications from the embedded and high performance computing domain
- Porting and optimization strategies for legacy applications

Submissions can either be full papers (up to 10 pages) or short papers with 4 pages. Authors of accepted full papers are expected to give a talk; short papers shall be presented on a poster during the workshop.

All papers will be processed in a peer review with at least 3 reviews for each paper.

Accepted papers of the workshop will be published in the GI Edition ? Lecture Notes in Informatics (LNI) series. Author guidelines as well as LaTeX and Microsoft Word templates can be downloaded here:

http://www.gi.de/service/publikationen/gi-edition-...