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WRC 2012 - 6th HiPEAC Workshop on Reconfigurable Computing
Topics/Call fo Papers
6th HiPEAC Workshop on Reconfigurable Computing
January 23-24, 2012
Paris, France
Authors are invited to electronically submit papers up to 10 pages in Springer LNCS format in the following website: papers upload link will be provided soon.
IMPORTANT DATES
Submission deadline: November 7, 2011
Notification of acceptance: November 30, 2011
Final version due: December 6, 2011
The main purpose of this workshop is to encourage the submission of work-in-progess in the topics covered by the call, thus providing quick and valuable feedback. As such we do not provide formal proceedigns. We encoruage authors of papers who want to timestamp immediately their idea to forward their paper to HiPEAC tech-report, after presentation at our workshop. Moreover, best papers will be selected and forwarded for possibile pubblication on Journal of Systems and Architectures - JSA.
The topics of interest include, but are not limited to:
Reconfigurable Architectures:
- Novel architectures (logic blocks, interconnects, I/O)
-Reconfigurable fabrics combined with dedicated system blocks (DSP, processors, memory etc.)
- Memory issues: adaptivity, coherence, latency tolerance, …
- Multicore support, resource sharing support, …
- Low power reconfigurable architectures, …
- Networks on chip tailored for reconfigurable architectures, …
- Dynamic and run-time reconfiguration,
- Defect and Fault Tolerance
Reconfigurable Tools and Technologies:
- System level design and HW/SW co-design
- Static and dynamic power efficiency
- Modeling, optimization, technology mapping and design verification
- Design and debug of reconfigurable systems
- Testing, verification and benchmarking
- Dedicated compilers and high-level languages
- Operating system support for reconfigurability
- Impact of reconfigurable hardware on real-time performance
Reconfigurable Applications and Algorithms:
- Adaptive and bio inspired applications
-Application domain specific, e.g. multimedia, bioinformatics, cryptography and more
- High-performance, high reliability and/or power efficient application acceleration
- Rapid prototyping
January 23-24, 2012
Paris, France
Authors are invited to electronically submit papers up to 10 pages in Springer LNCS format in the following website: papers upload link will be provided soon.
IMPORTANT DATES
Submission deadline: November 7, 2011
Notification of acceptance: November 30, 2011
Final version due: December 6, 2011
The main purpose of this workshop is to encourage the submission of work-in-progess in the topics covered by the call, thus providing quick and valuable feedback. As such we do not provide formal proceedigns. We encoruage authors of papers who want to timestamp immediately their idea to forward their paper to HiPEAC tech-report, after presentation at our workshop. Moreover, best papers will be selected and forwarded for possibile pubblication on Journal of Systems and Architectures - JSA.
The topics of interest include, but are not limited to:
Reconfigurable Architectures:
- Novel architectures (logic blocks, interconnects, I/O)
-Reconfigurable fabrics combined with dedicated system blocks (DSP, processors, memory etc.)
- Memory issues: adaptivity, coherence, latency tolerance, …
- Multicore support, resource sharing support, …
- Low power reconfigurable architectures, …
- Networks on chip tailored for reconfigurable architectures, …
- Dynamic and run-time reconfiguration,
- Defect and Fault Tolerance
Reconfigurable Tools and Technologies:
- System level design and HW/SW co-design
- Static and dynamic power efficiency
- Modeling, optimization, technology mapping and design verification
- Design and debug of reconfigurable systems
- Testing, verification and benchmarking
- Dedicated compilers and high-level languages
- Operating system support for reconfigurability
- Impact of reconfigurable hardware on real-time performance
Reconfigurable Applications and Algorithms:
- Adaptive and bio inspired applications
-Application domain specific, e.g. multimedia, bioinformatics, cryptography and more
- High-performance, high reliability and/or power efficient application acceleration
- Rapid prototyping
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Last modified: 2011-10-06 16:54:45